Carl Sechen

Power reduction via near-optimal library-based cell-size selection

Assuming continuous cell sizes we have robustly achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branch-and-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a typical library gives results close to the optimal continuous size results. After using state-of-the-art commercial synthesis, the application of our discrete size selection tool results in a dynamic power reduction of 40% (on average) for large industrial designs.

An efficient method for generating exhaustive test sets

We present a new algorithm for generating tests for single stuck line (SSL) faults in combinational logic circuits using a combination of Boolean and path-oriented techniques. We use Boolean techniques employing the ordered binary decision diagram (BDD) to limit the effect of hard faults on the performance of the algorithm. We use path-oriented techniques similar to those in conventional test generation algorithms to limit the number of algebraic operations that must be performed. The test set generated for each fault is exhaustive in the sense that we find all test patterns which make the fault observable at some primary output. We implemented the algorithm as the program TSUNAMI and applied it to the standard ISCAS 85 and ISCAS 89 benchmark circuits. Results indicate that for circuits which are amenable to analysis by BDDs, TSUNAMI performs significantly better than conventional algorithms such as FAN or EST in generating tests for all targeted faults. Moreover, TSUNAMI finds a large set of test vectors for each fault. The program can easily manipulate these sets of vectors to produce test vectors which test many faults. As a result, we are able to compress the sets of vectors into a very small total number of patterns.

Nonconvex Gate Delay Modeling and Delay Optimization

Convex delay models like the Elmore model, the related Logical Effort model, posynomial, and generalized posynomial models have always been favored by researchers, as convexity has a priori guarantees of global optimum solutions. The accuracy of the model may be sacrificed in this quest to generate convex delay models. In this paper, we investigate the use of signomial delay modeling for area/delay optimization. We present a procedure to automatically generate signomial gate delay models by nonlinear least squares fitting. As opposed to posynomial models, signomial models achieve better fits to SPICE generated data. However, signomials are not convex in general. Nevertheless, we show via duality arguments that we obtain near optimum (within 1%) solutions. Our optimization considers beta-ratio constraints, minimum and maximum size constraints for n- and p-transistors, rise/fall delays, and edge rates. The gate sizes for the fastest delay solution for a 44000-cell design, using the IBM 130-nm process, can be achieved in about 16 min of CPU time on a PC, and the area-delay tradeoff curve for 21 points can be generated in about 2 h of CPU time. To the best of our knowledge, this is the first report of using a true signomial delay model and its application to optimum gate sizing. In addition, we give performance details for the automatic data fitting for an 11-function library of static CMOS gates.

TonyChopper: a desynchronization package

TonyChopper is an integrated set of tools for digital circuit desynchronization. The core portion of TonyChopper is a tool that reads a gate-level synthesized synchronous digital circuit and transforms it to an asynchronous circuit by implementing a novel desynchronization approach. Pre-layout and post-layout verification tools are also provided in this package. The proposed new asynchronous design method is compatible with conventional synthesis, placement and routing (PnR) and other computer-aided design (CAD) tools. Only a conventional standard cell library is used. Compared to traditional synchronous static CMOS design, the proposed design is highly suitable for very low voltage operation. An auto-sleep strategy is also integrated in the tool for minimizing the leakage power for circuits. Different benchmark circuits were implemented in IBM 130nm technology to show that the design approach used in TonyChopper is highly robust even in the sub-threshold regime. The layout for every benchmark circuit was generated using a Cadence PnR tool. Hspice simulation for both the synchronous benchmark circuit and the desynchronized version provided comparison of the delay, area and leakage power for each benchmark circuit. Monte Carlo simulations were performed for each benchmark circuit to demonstrate high robustness and delay insensitivity for near threshold supply voltages with substantial threshold voltage (VT) variations.

A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic

We present a new approach for gate-level delay-insensitive asynchronous logic. The new approach uses only conventional synchronous synthesis and computer-aided design tools, as well as conventional standard cell libraries. This new design approach is highly suitable for very low voltage operation compared with traditional static CMOS design. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. Several benchmark circuits are implemented using IBM 130nm technology to show that the new asynchronous logic approach is robust even when operating in the sub-threshold regime. The layout for each benchmark is generated using Cadence’s automatic placement and routing tool. Hspice simulations for both asynchronous and synchronous versions of the benchmark circuits enabled comparison of the delay, area and leakage current. Monte Carlo simulations are performed for each benchmark circuit to demonstrate delay insensitivity for very low supply voltages with substantial threshold voltage (

Power reduction via separate synthesis and physical libraries

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A MEMS-Assisted Temperature Sensor With 20-

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We developed a new post-synthesis algorithm that minimizes leakage power while strictly preserving the delay constraint. A key aspect of the approach is a new threshold voltage (VT) assignment algorithm that employs a cost function that is globally aware of the entire circuit. Thresholds are first raised as much as possible subject to the delay constraint. To further reduce leakage, the delay constraint is then iteratively increased by Δ time units, each time enabling additional cells to have their threshold voltages increased. For each of the iterations, near-optimal cell size selection is applied so as to reacquire the original delay target. The leakage power iteratively reduces to a minimum, and then increases as substantial cell upsizing is required to re-establish the original delay target. We show results for benchmark and commercial circuits using a 40nm cell library in which four threshold voltage options are available. We show that the application of the new leakage power minimization algorithm appreciably reduces leakage power after multi-VT synthesis by a leading commercial tool, achieving an average post-synthesis leakage reduction of 37% while also reducing total active area and maintaining the original delay target.