Sudhakar Pamarti

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.

Replica compensated linear regulators for supply-regulated phase-locked loops

Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable tradeoffs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulators amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifiers gain to reject supply noise is effectively restored. Analysis shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised, and experimental results from a 90 nm SOI test chip confirm that with the same power consumption, the proposed regulator achieves at least 4 dB higher supply rejection than the previous regulator design. Furthermore, simulations show that if not for other supply rejection-limiting components in the PLL, the supply rejection improvement of the proposed regulator is greater than 15 dB.

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators

An analysis of the quantization noise introduced by a widely-used class of single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the quantization noise such as uniformity and independence from the input and delayed versions of itself. The conditions are also shown to be sufficient for a single realization of the quantization noise sequence to possess these properties in a time-averaged sense. Several of the most commonly-used digital DeltaSigma modulators are shown to satisfy the conditions

LSB Dithering in MASH Delta–Sigma D/A Converters

Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta-sigma (DeltaSigma) modulator in a multistage digital DeltaSigma modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dithers contribution to the power spectral density of the multistage digital DeltaSigma modulators output. A large class of popular multistage digital DeltaSigma modulators that satisfy the conditions are identified and tabulated for easy reference

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With

MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, a MEMS-based programmable oscillator is presented which achieves better than ±0.5-ppm frequency stability from -40°C to 85°C and less than 1-ps (rms) integrated phase noise (12 kHz to 20 MHz). A key component of this system is a thermistor-based temperature-to-digital converter (TDC) which enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high-resolution tunable reference resistor based on a switched-capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. The TDC achieves 0.1-mK (rms) resolution within a 5-Hz bandwidth while consuming only 3.97 mA for all analog and digital circuits at 3.3-V supply in 180-nm CMOS.

Frequency Stability and

The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N PLLs and quantization noise and fractional spur suppression techniques for wide-bandwidth applications.

Integrated Jitter

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (-40 °C to 85 °C) is ±100 ppm as an oscillator (XO) or ±3 ppm with optional calibration as a temperature compensated oscillator (TCXO). Supply currents are 0.9 μA for the XO and 1.0 μA for the TCXO at supply voltages from 1.4 V to 4.5 V. The MEMS resonator is a capacitively-transduced tuning fork at 524 kHz. The circuitry is fabricated in 180 nm CMOS and includes low power sustaining circuit, fractional-N PLL, temperature sensor, digital control, and low swing driver.

Fractional-

A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-N phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional-N PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented.

N

MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency with temperature and process. We present several techniques enabling efficient implementation of this synthesizer, including a switched-resistor loop filter topology that avoids a charge pump and boosts effective resistance to save area, a high gain phase detector that lowers the impact of loop filter noise, and a switched capacitor frequency detector that provides initial frequency acquisition. The entire synthesizer with LC VCO occupies less than 0.36sq. mm in 0.18 m CMOS. Chip power consumption is 3.7 mA at 3.3 V supply (20 MHz output, no load).