Carlos Augusto de Moraes Cruz

FPN Attenuation by Reset-Drain Actuation in the Linear-Logarithmic Active Pixel Sensor

The three FET CMOS active pixel sensors (APS) operating in the linear-logarithmic mode is one of the most efficient wide-dynamic-range imagers. However, the quality of the image generated at the focal-plane array is often compromised by fixed-pattern noise (FPN) between pixels. The classical correlated double sampling (CDS) technique is used to reduce FPN in imagers operating in the linear mode. But in the complementary linear-logarithmic mode CDS does not work properly and alternative techniques must be applied to reduce FPN. The ordinary alternative techniques increase either the complexity of the pixel or its external circuitry. In order to avoid these problems a new technique was devised to reduce FPN that can be applied to the basic three FET APS architecture. With the purpose to assert the efficacy of the proposed technique a small array was fabricated in a standard 0.35 μm CMOS technology. Experimental results show that the proposed technique is able to reduce FPN quite steadily within the whole illumination range used to test the array. And therefore, the signal-to-noise-and-distortion ratio (SNDR) of the array is also improved within the whole range of operation.

A charge pump without overstress for standard cmos process with improved current driver capability

Many charge pump structures that overcome gate-oxide overstress have been proposed in the last few years. Though they differ in the number of phases and in efficiency, they have almost the same current driver capability. A new charge pump without gate-oxide overstress, with a better current driver capability is proposed here. The new circuit is derived from a two-phase charge pump in order to inherit its efficiency. A four-stage structure of the proposed circuit has shown a driver current capability 40% better than the previous solutions. The proposed circuit is also faster than the previous charge pumps that overcome gate-oxide overstress.

A charge pump circuit without gate-oxide overstress for standard CMOS technology and suitable for low-power applications

In the last years the gate-oxide overstress has become a great concern for CMOS circuits and even more so for circuits such as charge pumps. A new charge pump circuit that overcomes the gate-oxide overstress problem and has improved efficiency is proposed in this work. Simulations have shown that for 1¿A current load a four-stage structure of proposed circuit reaches efficiency of about 64%, what is almost three times the efficiency of previous solutions in the same conditions. The better efficiency makes this circuit more suitable for low-power applications. Measurements have shown that a four-stage structure of the new circuits yields a pumping efficiency of 98.12%.

Voltage Mode FPN Calibration in the Logarithmic CMOS Imager

The CMOS active pixel sensor (APS) operating in the logarithmic mode is the most common and useful CMOS wide-dynamic-range imager. Notwithstanding, fixed-pattern noise (FPN) between pixels compromises the quality of the image generated by the focal-plane array. Classical techniques as correlated double sampling do not work properly in this mode, and alternative techniques must be applied in order to calibrate FPN. The alternative techniques require either complex pixel circuitry, or external memory and software level calibration. Purposefully to improve image quality at reduced circuitry complexity, a new calibration technique is proposed that can be applied directly to the basic three-FET APS circuit. The efficacy of the proposed technique was experimentally verified with a small pixel array fabricated in a standard 0.35-

MAGFET with embedded Gilbert gain cell

\mu \text{m}

Improved Charge Pump Circuits for Standard CMOS Technologies

CMOS technology. The experimental results show a steady FPN attenuation within the whole tested illumination range and the improvement of the signal-to-noise and distortion ratio of the array.

Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response

A modified Gilbert gain cell implemented with lateral-PNP transistors has been successfully used to amplify the output current signal from an N-channel split-drain MOS transistor, or MAGFET. Compared with other previously reported signal conditioning circuits for MAGFETs, the herein presented approach adds the advantage of featuring programmability for the current gain, thus providing means of controlling the sensitivity of the magnetic detecting device. Measurements of prototypes of the circuit, fabricated in 0.35mum CMOS, have proved the concept.

A novel hybrid polarization-quadrature pixel cluster for local light angle and intensity detection

Reliability problems such as gate-oxide voltage overstress have become a concern for CMOS circuits as the gate-oxide thickness is scaled down. Gate-oxide overstress is particularly worse for charge pump circuits because they usually operate in high voltage levels. Devising charge pump circuits that avoid such problem is far simpler for CMOS triple well technologies than for standard technologies, nevertheless fabrication costs are higher. Two approaches are usually applied to eliminate gate-oxide overstress in charge pumps designed for standard CMOS technologies, the first is multiple phase control, and the second is dual phase control with doubled voltage swing. The latter has been shown to produce more power efficient circuits, however solutions using such approach still present gate-oxide overstress in some transistors. In this work a simple solution is presented which is shown to be able to overcome the problem. Moreover, simulations have shown that the proposed circuits can reach about 98.2% of voltage multiplication efficiency.Reliability problems such as gate-oxide voltage overstress have become a concern for CMOS circuits as the gate-oxide thickness is scaled down. Gate-oxide overstress is particularly worse for charge pump circuits because they usually operate in high voltage levels. Devising charge pump circuits that avoid such problem is far simpler for CMOS triple well technologies than for standard technologies, nevertheless fabrication costs are higher. Two approaches are usually applied to eliminate gate-oxide overstress in charge pumps designed for standard CMOS technologies, the first is multiple phase control, and the second is dual phase control with doubled voltage swing. The latter has been shown to produce more power efficient circuits, however solutions using such approach still present gate-oxide overstress in some transistors. In this work a simple solution is presented which is shown to be able to overcome the problem. Moreover, simulations have shown that the proposed circuits can reach about 98.2% of voltage multiplication efficiency.

Power consumption contrasting model for different logarithmic active pixel sensor topologies

The pseudo-flash reset (P-FRST) is a technique used to reduce image lag in CMOS active-pixel sensors (APS). The compact pixel topology consisting of a photodetector and three FETs (3T APS) is widely employed because of its large fill factor combined with the possibility to operate in both linear and logarithmic compressed-response (LCR) modes. The use of these two modes in a single readout cycle yields good low-light sensitivity and extended dynamic range (DR). However, fabrication non idealities result in fixed-pattern noise (FPN) across the image-sensor chip and cannot be reduced by classical double-sampling readout subtraction (DSRS). In the present work, we propose an extended use of the P-FRST technique to provide an adequate voltage reference on pixel, in order to enable DSRS, thus reducing FPN in conventional 3T APS operating in mixed linear-LCR mode.

A low-power FPN attenuation method in the double-log PMOS APS

Detecting local light incident angle is a desirable feature for CMOS image sensors for 3D image reconstruction purposes. Advances in the CMOS technologies in the last years have enabled integrated solutions to perform such a job. However, it is still not viable to implement such a feature in regular CMOS image sensors due to the great number of pixels in a cluster to perform incident angle detection. In this paper, a hybrid cluster with only four pixels, instead of eight pixels of previous solutions, that is able to detect both local light intensity and incident angle. The technique to detect local incident angle is widely exploited in the literature. Two novelties are explored in this work, the first is the new paradigm in polarization cluster-pixel design and the second is the extended ability of metal shielded pixels to detect both the local light angle and intensity. SPICE simulation results show that the existing Quadrature Pixel Cluster — QPC and Polarization Pixel Cluster — PPC models are in accordance with experimental results presented in the literature, and thus it was possible to demonstrate similar behavior in the new proposed pixel cluster.