Carlos Alberto dos Reis Filho

A charge pump without overstress for standard cmos process with improved current driver capability

Many charge pump structures that overcome gate-oxide overstress have been proposed in the last few years. Though they differ in the number of phases and in efficiency, they have almost the same current driver capability. A new charge pump without gate-oxide overstress, with a better current driver capability is proposed here. The new circuit is derived from a two-phase charge pump in order to inherit its efficiency. A four-stage structure of the proposed circuit has shown a driver current capability 40% better than the previous solutions. The proposed circuit is also faster than the previous charge pumps that overcome gate-oxide overstress.

A charge pump circuit without gate-oxide overstress for standard CMOS technology and suitable for low-power applications

In the last years the gate-oxide overstress has become a great concern for CMOS circuits and even more so for circuits such as charge pumps. A new charge pump circuit that overcomes the gate-oxide overstress problem and has improved efficiency is proposed in this work. Simulations have shown that for 1¿A current load a four-stage structure of proposed circuit reaches efficiency of about 64%, what is almost three times the efficiency of previous solutions in the same conditions. The better efficiency makes this circuit more suitable for low-power applications. Measurements have shown that a four-stage structure of the new circuits yields a pumping efficiency of 98.12%.

Shunt-Zero Based on CMOS Split-Drain: A Practical Approach for Current Sensing

A current sensor circuit intended for integrated smart-power applications featuring galvanic isolation is devised. It is based on magnetic detection using the CMOS compatible split-drain transistors (MAGFET) that provides linear output current versus magnetic field from DC to several MHz range. An integrated sensor built in 0.35 mum CMOS technology presented an output conversion factor of 500 nA/A, corner frequency around 1 MHz and thermal spectral density of 60 pA/radicHz for a power dissipation of less than 15 mW

CMOS bandgap with base-current thermal compensation

This paper describes a CMOS bandgap voltage reference, which features a curvature compensation that is based on the thermal behavior of the base current. The core of the circuit uses vertical bipolar transistors and high resistive poly resistors (RPOLYH), as most currently implemented CMOS bandgap circuits, however arranged in a novel configuration. A three-bit digital trimming mechanism was incorporated in the circuit to adjust the reference voltage to its minimum TC value. Samples of the circuit were fabricated in 0.6 /spl mu/m CMOS. Measurements in the range -40/spl deg/C to +120/spl deg/C showed that the temperature drift is less than 23 ppm//spl deg/C.

A High-Speed Low-Distortion CMOS Source Follower Buffer

This paper discusses the design and implementation of a pseudo-differential high-speed and highly linear novel Source-Follower Buffer in 0.35 μm CMOS. The high linearity of Source Follower is achieved by means of a cascode transistor and an auxiliary structure to mitigate impact of channel modulation and parasitic capacitances. The new architecture consumes 10 mW from a 3.3-V supply and it achieves a total harmonic distortion of -74.5 dB at 100 MHz, yielding 12-b resolution. Design methodology, simulation and experimental results are presented.

New 12-bit source-follower track-and-hold circuit suitable for high-speed applications

An analysis of a cascode source-follower with all transistors operating in saturation mode is presented. The new structure provides means to mitigate the effects of nonlinearities caused by transistor capacitances. It is also studied the effects of adding a sampling switch at the output of the source-follower. Performance results of 0.35µm CMOS implementation and dimensioning methodology of the resulting source sampling circuit is presented along the text. The circuit achieves more than 12 bits of linearity in the frequencies from 0 to 100MHz while consuming 10mW.

A -60dB THD/100MHz true unity-gain voltage buffer CMOS circuit

In this paper an open-loop CMOS voltage buffer is unveiled which features less than -60dB THD within a bandwidth of 100MHz and large-signal gain that departs from unity a maximum of 1.6% within the band. Design methodology and proof-of-concept simulation results of an implementation in 0.35um CMOS are presented.

Temperature-related voltage generating circuit using MOS in strong inversion

System-on-Chip (SoC) integrated circuits frequently embed voltage references and temperature sensors. In view of the spread of battery-supplied products, there is a growing demand for low-power and low-voltage circuit solutions to implement these blocks. This paper describes the development of one such circuit structure that employs an alternative technique to generate reference and PTAT voltage signals based on a suitable arrangement of MOS transistors operating in strong inversion. Low-voltage prototypes were produced on the conventional process CMOS AMS 0.35um to provide the experimental results presented in this work. These results include the generation of a voltage reference signal with thermal coefficient lower than 10ppm/°C, from −40°C to 120°C, under a 1V power supply.

Latency evaluation in a Bluetooth-CAN dual media sensor network

In this paper, a system is described which implements the communication between a controller area network (CAN) bus and wireless Bluetooth (BT) networks. The importance of such a system stems from the widespread use of CAN in industrial automation and the growing interest for deploying wireless sensor and actuator networks at the same environment. CAN is known for its robustness and reliability while wireless networks drastically reduce costs and the efforts of installation and configuration. Among the many wireless network technologies available at this date, Bluetooth is neither the fastest nor the cheapest solution, but it complies with the requirements of robustness that industrial applications impose. The developed system forms a data communication environment that comprises two distinct networks, which are interconnected by a bridge-like structure that allows data from sensors that are connected to a CAN bus to be available at the BT network and vice-versa. The latencies due to the interaction between the two different protocols were identified and studied in order to implement a reliable, efficient and satisfactory network of sensors and actuators. Measurement results from an experimental implementation of the system is presented and discussed. An important conclusion from the obtained results is that for high baud rates, average latency is less than 10ms and jitter is less than 2ms, thus showing that the dual media network is a competitive solution for industrial automation.

A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction

This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSIM II simulator on the AMS CMOS 0.8 /spl mu/m CYE and they reveal the circuit has a reduced error of just 0.03% at the output.