Carlos Dualibe

Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all

A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the g/sub m//I/sub D/ methodology. It is shown that this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and rise time) for a 6 bits accuracy and a typical consumption of 50 /spl mu/W/cell than previous realisations.

A 5.26 Mflips programmable analogue fuzzy logic controller in a standard CMOS 2.4 /spl mu/ technology

A complete digitally-programmable analogue fuzzy logic controller (FLC) is presented. The design of some new functional blocks and the improvement of others aim towards speed optimisation with a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4 /spl mu/ technology showing good agreement with the expected performances, namely: 5.26 Mflips (mega fuzzy logic inferences per second) at the pin terminal (@CL=13 pF), 933 /spl mu/W power consumption per rule (@Vdd=5V) and 5 to 6 bits of precision. Since the circuit is intended for a subsystem embedded in an application chip (@CL/spl les/15 pF) over 8 Mflips may be expected.

A current-mode CMOS loser-take-all with minimum function for neural computations

A novel architecture for loser-take-all functions is proposed. Inputs and outputs of the circuit are currents, which make the circuit appropriated for low-voltage neural hardware computation. In contrast to most existing realisations the circuit does not require subtraction from a fixed reference which decreases accuracy and input dynamic. Moreover, in addition to the loser, it also outputs the minimum input current. The circuit was synthesized using a SOI (silicon on insulator) technology and optimised to work with 1.5 V voltage supply showing improved speed and accuracy for a very low power consumption (typically 5 /spl mu/W per cell when the input current is 1 /spl mu/A).

Embedded fuzzy control for automatic channel equalization after digital transmissions

A straightforward technique for automatic adaptation of channel equalizers after digital data transmission is presented. Inter-Symbol Interference (ISI) at the received signal is identified by scanning the input stream over time at the data clock frequency. The resulting 2D-figure is compared against an ideal opened Eye Pattern encoded into a two-input one-output analogue Fuzzy Inference System. Any deviation from the reference eye results in an error-signal used to properly locate the symmetric zeros of an analogue amplitude-equalizer biquad gm-c filter intended for the inversion of the channel transfer function. The adaptation can work on-line during transmission and no reference signal is required. The presented methodology was validated by simulations for cable equalization wherein the controller as well as the filter were modeled with their actual measured features drawn from a fabricated CMOS prototype. The system shows self-adapting capabilities for diverse cable length settings and the ISI is removed in all cases.

A new CMOS voltage reference scheme based on Vth-difference principle

A new CMOS voltage reference, which takes advantage of the temperature dependence of NMOS and PMOS threshold voltages, is presented. Due to the circuit architecture the mobility factor is completely cancelled. It does not use resistors and all transistors works in strong inversion. The circuit is simple, opamp-less and can be implemented in a standard CMOS process. When the input power supply changes from 1.8V to 2.1V and the temperature changes from -20 to 80degC, simulations for the reference circuit using the proposed architecture shows an output voltage of 1.184V and a TFC of 100 ppm/degC.

A 9.6 kb/s CMOS FSK modem for data transmission through power lines

The design and test of a mixed-signal 9.6Kb/s FSK transmitter-receiver is presented. It is aimed for digital communications through the domiciliary power lines as needed by a networked electrical power management and measuring system wherein the circuit must be embedded. For the desired baud rate the bit carriers frequencies of 111KHz (logical 0) and 125KHz (logical 1) were found optimal. The receiver amplifies and demodulates the incoming bit stream following a frequency-domain discrimination strategy based on switched capacitor (SC) filtering. The transmitter, pure digital, generates the carriers tones and builds the outgoing bit stream based on a frequency division technique by means of digital counters driven by a 6 MHz master clock. This can be either externally or internally generated and, as a byproduct, it is also used to handle the switches of the SC filters in the receiver. The circuit was fabricated in a standard 1.6um CMOS technology. For a ±2.5V rail-to-rail power supply the die area results in 5.76 mm2 whereas the current consumption is kept below 12mA. The modem was successfully tested within its own working environment. Main advantages with respect to its previously implemented discrete version by the OEM[1] reside in the extremely reduced number of external components required and the needlessness of a-posteriori filter tuning.

Design and Application of Analog Fuzzy Logic Controllers

Fuzzy logic has been successfully applied to solve problems in many fields: the classical control, power control, signal and image processing, for instance. As these kinds of application need real-time processing mode, faster, more autonomous and less power-consuming circuits, the choice of on-chip controllers becomes an interesting option. The attractiveness of analog circuits for implementing fuzzy hardware relies on its natural compatibility with most used fuzzy algorithms and the needlessness of A/D and D/A converters for interfacing sensors and actuators. This chapter deals with the implementation of programmable analog fuzzy logic controllers in CMOS technologies.