Walter J. Lancioni
Catholic University of Cordoba
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Walter J. Lancioni.
international symposium on circuits and systems | 2007
Luis Eduardo Toledo; Walter J. Lancioni; Pablo A. Petrashin; Carlos Dualibe; Carlos Daniel Vázquez
A new CMOS voltage reference, which takes advantage of the temperature dependence of NMOS and PMOS threshold voltages, is presented. Due to the circuit architecture the mobility factor is completely cancelled. It does not use resistors and all transistors works in strong inversion. The circuit is simple, opamp-less and can be implemented in a standard CMOS process. When the input power supply changes from 1.8V to 2.1V and the temperature changes from -20 to 80degC, simulations for the reference circuit using the proposed architecture shows an output voltage of 1.184V and a TFC of 100 ppm/degC.
latin american symposium on circuits and systems | 2013
Luis Eduardo Toledo; Pablo A. Petrashin; Walter J. Lancioni; Fortunato Dualibe; Luis Rafael Canali
A novel scheme for a CMOS low-voltage reference is proposed. It uses current subtraction between the currents generated by two instances of the same current generator circuit, each one configured with different magnitude and temperature coefficients. Temperature stability is achieved owing to the partial compensation of the MOSFET threshold voltage and mobility temperature effects. For a nominal reference voltage of 436.5 mV, SPICE simulation reveals a ±38.2 ppm/°C temperature coefficient within the range of -20 °C to 100°C.
latin american symposium on circuits and systems | 2015
Luis Eduardo Toledo; Pablo A. Petrashin; Walter J. Lancioni; Carlos Daniel Vázquez
The threshold voltage (Vth) is a key parameter in MOSFET design and modeling. There are many definitions and extraction methods, each one given with a focus on different aspects. This work presents a simple circuit that extracts the threshold voltage under low voltage conditions and using a feedback loop in order to reach supply independence. The circuit has been simulated using the BSIM3v3 model for a 0.18μm CMOS process. The extracted value of VTHN is very close to the model nominal value (VTHO) used from the model parameters being the variation of +0.327% and -0.294% from VDD=0.6V to VDD=3V. The bias current I is from 810.7nA to 872nA for the same supply voltage variation.
latin american test workshop - latw | 2013
Pablo A. Petrashin; Carlos Dualibe; Walter J. Lancioni; Luis Eduardo Toledo
This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.
Vlsi Design | 2017
Pablo A. Petrashin; Luis Eduardo Toledo; Walter J. Lancioni; Piotr J. Osuch; Tinus Stander
The Argentina-South Africa Research Cooperation Programme, as administered by the Ministry of Science, Technology and Productive Innovation in Argentina and the National Research Foundation in South Africa.
2015 16th Latin-American Test Symposium (LATS) | 2015
Carlos Viale; Pablo A. Petrashin; Luis Eduardo Toledo; Walter J. Lancioni; Carlos Daniel Vázquez
The present work studies the response to an Analog Single Event Transient (ASET) of a Silicon-on-insulator (SOI) OTA. By adopting an ASET model previously reported and fully compatible with SPICE descriptions, a simulation campaign is carried out in the SOI OTA taken as case study. SOI technology happens to be well suited for radiation-hardened applications and is rapidly becoming a main-stream commercial technology. However, one of the main reasons for the rapid degradation of commercial ICs in space is the natural radiation environment present there. The faults caused by the passing of a high energy particle through the circuit are called Single Event Effects (SEEs). This study identifies the most sensitive transistors that should be hardened in order to improve the behavior in the system-level.
argentine school of micro-nanoelectronics, technology and applications | 2014
José Ducloux; Pablo A. Petrashin; Walter J. Lancioni; Luis Eduardo Toledo
At the present, the digital TV allows the access to a greater amount of content and to execute interactive applications. The remote control used to control the digital TV systems is, in most cases, still solved by the traditional infrared remote control, which has become a limiting factor on the user interaction with the TV. This paper introduces the design and development of an interaction device for use in the context of digital TV in Argentina. The proposed device can be considered an evolution of the classic remote control, in which the functionality of hand gesture recognition is implemented as a natural and friendly interface for controlling digital TV systems of the home. A gestural dictionary of 20 types of gestures was adopted. The recognized gestures are translated into control commands for digital TV systems. As the hand gesture recognition is a pattern classification problem, two techniques based on artificial neural networks were explored, in order to compare results and to select the tool that best fits the problem in question. The pattern classifier design was described in detail, in order to properly select the hardware platform, fulfilling requirements of low-cost and fast execution of pattern classification algorithms. An interaction device of low-cost and excellent recognition precision was developed, for enhancing and enriching the user experience.
symposium on integrated circuits and systems design | 2007
Walter J. Lancioni; Pablo A. Petrashin; Luis Eduardo Toledo; Carlos Dualibe
The design and test of a mixed-signal 9.6Kb/s FSK transmitter-receiver is presented. It is aimed for digital communications through the domiciliary power lines as needed by a networked electrical power management and measuring system wherein the circuit must be embedded. For the desired baud rate the bit carriers frequencies of 111KHz (logical 0) and 125KHz (logical 1) were found optimal. The receiver amplifies and demodulates the incoming bit stream following a frequency-domain discrimination strategy based on switched capacitor (SC) filtering. The transmitter, pure digital, generates the carriers tones and builds the outgoing bit stream based on a frequency division technique by means of digital counters driven by a 6 MHz master clock. This can be either externally or internally generated and, as a byproduct, it is also used to handle the switches of the SC filters in the receiver. The circuit was fabricated in a standard 1.6um CMOS technology. For a ±2.5V rail-to-rail power supply the die area results in 5.76 mm2 whereas the current consumption is kept below 12mA. The modem was successfully tested within its own working environment. Main advantages with respect to its previously implemented discrete version by the OEM[1] reside in the extremely reduced number of external components required and the needlessness of a-posteriori filter tuning.
latin american symposium on circuits and systems | 2017
Pablo A. Petrashin; Luis Eduardo Toledo; Walter J. Lancioni; Piotr J. Osuch; Tinus Stander
Oscillation based testing (OBT) has proven to be a simple yet effective VLSI test for numerous circuit types. In this work, OBT is applied to test Second-generation Current Conveyor (CCII) based filters for the first time. Adopting a CCII-based band pass filter as a case study, it is shown that OBT can be implemented with a minimally intrusive switched feedback loop to establish the oscillator. Exhaustive fault simulation indicates 98.11% detection of possible short circuit and 100% detection of possible open circuit faults in the circuit under test, in both 0.35μm and 1.2μm CMOS technology nodes.
argentine school of micro-nanoelectronics, technology and applications | 2012
J. Ducloux; Pablo A. Petrashin; Walter J. Lancioni; Luis Eduardo Toledo