Carlos H. Llanos

FPGA based floating-point library for CORDIC algorithms

Computation of floating-point transcendental functions has a relevant importance in a wide variety of scientific applications, where the area cost, error and latency are important requirements to be attended. This paper describes a flexible FPGA implementation of a parameterizable floating-point library for computing sine, cosine, arctangent and exponential functions using the CORDIC algorithm. The novelty of the proposed architecture is that by sharing the same resources the CORDIC algorithm can be used in two operation modes, allowing it to compute the sine, cosine or arctangent functions. Additionally, in case of the exponential function, the architectures change automatically between the CORDIC or a Taylor approach, which helps to improve the precision characteristics of the circuit, specifically for small input values after the argument reduction. Synthesis of the circuits and an experimental analysis of the errors have demonstrated the correctness and effectiveness of the implemented cores and allow the designer to choose, for general-purpose applications, a suitable bit-width representation and number of iterations of the CORDIC algorithm.

A suitable FPGA implementation of floating-point matrix inversion based on Gauss-Jordan elimination

This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA with single-precision floating-point representation, whose main unit is the processing component for Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized to maintain the accuracy of the results without the need to internally normalize and de-normalize the floating-point data. The implementation of the operations and the whole unit take advantage of the resources available in the Virtex-5 FPGA. The performance and resource consumption of the implementation are improvements in comparison with different more elaborated architectures whose implementations are more complex for low cost applications. Benchmarks are done with solutions implemented previously in FPGA and software, such as Matlab.

Parameterizable floating-point library for arithmetic operations in FPGAs

Floating-point operations are an essential requisite in a wide range of computational and engineering applications that need good performance and high precision. Current advances in VLSI technology raised the density integration fast enough, allowing the designers to develop directly in hardware several floating-point operations commonly implemented in software. Until now, most of the research has not focused on the tradeoff among the need of high performance and the cost of the size of logic area, associated with the level of precision, parameters that are very important in a wide variety of applications such as robotics, image and digital signal processing. This paper describes an FPGA implementation of a parameterizable floating-point library for addition/subtraction, multiplication, division and square root operations. Architectures based on Goldschmidt algorithm were implemented for computing floating-point division and square root. The library is parameterizable by bit-width and number of iterations. An analysis of the mean square error and the cost in area consumption is done in order to find, for general purpose applications, the feasible bit-width representation, number of iterations and number of addressable words for storing initial seeds of the Goldschmidt algorithm.

Background subtraction algorithm for moving object detection in FPGA

Currently, both the market and the academic communities have required applications based on image and video processing with several real-time constraints. On the other hand, detection of moving objects is a very important task in mobile robotics and surveillance applications. In order to achieve an alternative design that allows for rapid development of real time motion detection systems, this paper proposes a hardware architecture for motion detection based on the background subtraction algorithm, which is implemented on FPGAs (Field Programmable Gate Arrays). For achieving this, the following steps are executed: (a) a background image (in gray-level format) is stored in an external SRAM memory, (b) a low-pass filter is applied to both the stored and current images, (c) a subtraction operation between both images is obtained, and (d) a morphological filter is applied over the resulting image. Afterward, the gravity center of the object is calculated and sent to a PC (via RS-232 interface). Both the practical results of the motion detection system and synthesis results have demonstrated the feasibility of FPGAs for implementing the proposed algorithms on an FPGA based hardware platform. The implemented system provides one processed pixel per FPGAs clock cycle (after the latency time) and speed-ups the software implementation (using the real-time xPC Target OS from MathWorks) by a factor of 32.

Comparison between two FPGA implementations of the Particle Swarm Optimization algorithm for high-performance embedded applications

Particle Swarm Optimization (PSO) algorithms have been proposed to solve engineering problems that require to find an optimal point of operation. There are several embedded applications which requires to solve online optimization problems with a high performance. However, the PSO suffers on large execution times, and this fact becomes evident when using Reduced Instruction Set Computer (RISC) microprocessors in which the operational frequencies are low in comparison with the high operational frequencies of traditional personal computers (PCs). This paper compares two hardware implementations of the parallel PSO algorithm using an efficient floating-point arithmetic which perform computations with large dynamic range and high precision. The full-parallel and the partially-parallel PSO architectures allow the parallel capabilities of the PSO to be exploited in order to decrease the running time. Three well-known benchmark test functions have been used to validate the hardware architectures and a comparison in terms of cost in logic area, quality of the solution and performance is reported. In addition, a comparison of the execution time between the hardware and two C-code software implementations, based on a Intel Core Duo at 1.6GHz and a embedded Microblaze microprocessor at 50MHz, are presented.

Hardware Architecture for Particle Swarm Optimization Using Floating-Point Arithmetic

High computational cost for solving large engineering optimization problems point out the design of parallel optimization algorithms. Population based optimization algorithms provide parallel capabilities that can be explored by their implementations done directly in hardware. This paper presents a hardware implementation of Particle Swarm Optimization algorithms using an efficient floating-point arithmetic which performs the computations with high precision. All the architectures are parameterizable by bit-width, allowing the designer to choose the suitable format according to the requirements of the optimization problem. Synthesis and simulation results demonstrate that the proposed architecture achieves satisfactory results obtaining a better performance in therms of elapsed time than conventional software implementations.

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Many algebraic operations can be efficiently implemented as pipe networks in arrays of functional units such as systolic arrays that provide a large amount of parallelism. However, the applicability of classical systolic arrays is restricted to problems with strictly regular data dependencies yielding only arrays with uniform linear pipes. This limitation can be circumvented by using reconfigurable systolic arrays or reconfigurable data path arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative reconfigurable systolic architectures can be explored and powerful tools are needed to model and evaluate them. Well-known rewriting-logic environments such as ELAN and Maude can be used to specify and simulate complex application-specific integrated systems. In this article we propose a methodology based on rewriting-logic which is adequate to quickly model and evaluate reconfigurable architectures (RA) in general and, in particular, reconfigurable systolic architectures. As an interesting case study we apply this rewriting-logic modeling methodology to the space-efficient treatment of the Fast-Fourier Transform (FFT). The FFT prototype conceived in this way, has been specified and validated in VHDL using the Quartus II system.

Modeling a reconfigurable system for computing the FFT in place via rewriting-logic

The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the fast Fourier transform (FFT) using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.

A fast and low cost architecture developed in FPGAs for solving systems of linear equations

This paper presents a low cost architecture for the solution of linear equations based on the Gaussian Elimination Method using a reconfigurable system based on FPGA. This architecture can handle single data precision that follows the IEEE 754 floating point standard. The implementation takes advantage of both the internal memory and the DSP blocks (available in the Virtex-5 FPGA). The architectural approach is composed of four modules and one specific unit (namely, Change Row Module, Pivo Module, FB Module, Normalization Module and finally the Gaussian Elimination Controller Unit). This structure can be combined with other smaller arithmetic units in order to maintain the accuracy of the results without the need to internally normalize and de-normalize the floatingpoint data. Also, a special Memory Access Unit was implemented in order to deal with the writing/reading operations to/from the internal RAM. The resource consumption of the implementation (specially the internal RAM memory blocks that are used) points out several improvements when compared to previous work of the authors and other more elaborated architectures whose implementations are significantly more complex and, thus, unsuitable for low cost applications.

A GMDH polynomial neural network-based method to predict approximate three-dimensional structures of polypeptides

Tertiary Protein Structure Prediction is one of the most important problems in Structural Bioinformatics. Along the last 20years many algorithms have been proposed as to solve this problem. However, it still remains a challenging issue because of the complexity and of the dimensionality of the protein conformational search space. In this article a first principle method which uses database information for the prediction of the 3-D structure of polypeptides is presented. The technique is based on the Group Method of Data Handling (GMDH) algorithm, implemented by a software tool introduced on this work. GMDH Polynomial Neural Networks have been used with success in many fields such as data mining, knowledge discovery, pattern recognition and prediction. The proposed method was tested with seven protein sequences whose sizes vary from 14 to 54 amino acid residues. Results show that the predicted tertiary structures adopt a fold similar to the experimental structures. RMSD and secondary structure analysis reveal that the proposed method present accurate results in their predictions. The predicted structures can be used as input structures in refinement methods based on molecular mechanics (MM), e.g. molecular dynamics (MD) simulations. The search space is expected to be greatly reduced and the ab initio methods can demand a much reduced computational time to achieve a more accurate polypeptide structure.