Carroll Speir

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration

Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the system design. We describe a 16b ADC with a sample rate up to 250MS/s that employs background calibration of the residue amplifier (RA) gain errors. The ADC has an integrated input buffer and is fabricated on a 0.18µm BiCMOS process. When the input buffer is bypassed, the SNR is 77.5dB and the SFDR is 90dB at 10MHz input frequency. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The ADC consumes 850mW from a 1.8V supply, and the input buffer consumes 150mW from a 3V supply. The input span is 2.6Vp-p and the jitter is 60fs.

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break the dependence of the calibration on the input signal amplitude. In addition, to improve the sampling linearity, the ADC employs input distortion cancellation and another digital calibration to compensate for the non-linear charge injection (kickback) from the sampling capacitors on the input driver. The ADC is fabricated in a 65nm CMOS process and has an integrated input buffer. With a 140MHz and 2Vpp input signal, the SNR is 69dB, the SFDR is 86dB, and the power is 1.2W.

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology

Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of −157dBFS/Hz (i.e. DR = 60dB) while dissipating 2.9W.

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]

An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth (BW). An automatic-gain-control (AGC) loop is placed around the analog-to-digital converter (ADC). Amplitude-modulation (AM) caused by gain switching is corrected digitally.