Frank Murden

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.

A 14-bit 100-Msample/s subranging ADC

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W.

12b 50MSample/s two-stage A/D converter

A 12 b 50 MSample/s two-stage A/D converter in a complementary bipolar process uses coarse and fine encoders based upon a cascaded magnitude amplifier design. The ADC provides 80 dB SFDR for a 20 Mz analog input at 50MSPS while dissipating only 575 mW. Compared to other pipeline ADCs, a two-stage subranging flash architecture minimizes the number of analog and digital pipeline delays, but requires a large number of comparators in the coarse and fine flash converters to implement a high-resolution design. An architecture to implement the coarse and fine A/D converters requires only eleven absolute value or magnitude amplifiers, referred to as magamps, to realize a 12 b 50 MSample/s two-stage sub-ranging ADC. The gain alignment of the coarse and fine converters and the subtraction DAC rely on the statistical matching of the process, and 12 b linearity is obtained without laser trim. The ADC is fabricated on a high-speed dielectrically isolated complementary bipolar process that allows for more than 80 dB harmonic suppression up to an analog input frequency of 20 MHz while keeping the total ADC power dissipation at 575 mW from a single +5 V supply.

A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC

The high channel count of many modern communication systems increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/s with a 10MHz input. With a 200MHz input, the ADC achieves 71.0dBFS SNR, 69.4dBFS SNDR and 81dBc SFDR. The complete ADC including reference, clock, and digital circuitry consumes 100mW from a 1.8V supply. This compares favorably with recently reported ADCs in this performance class [1–3]. In this paper, several architectural and circuit techniques used to achieve this performance are presented. The techniques include a dynamically driven deep N-well input sampling switch, an offset-cancelled comparator, and a back-gate voltage-biased MDAC amplifier. The ADC is fabricated in a 1P5M 0.18μm CMOS process with deep N-well (DNW) isolation.

A 14b 100MSample/s 3-stage A/D converter

A 14b three-stage ADC uses a complementary bipolar process to achieve a 100MSample/s encode rate with a SFDR of >90 dB and an SNR of 75 dB. While the design is based on a traditional multi-stage architecture, the three encoder stages use serial-ripple converters. Unlike the typical N-bit flash converter which requires 2-/sup N-1/ comparators, the serial-ripple converter has only N comparators. The result is a smaller die area and lower power dissipation than flash. This design uses a total of 16 comparators, and at the full sample rate consumes 1250 mW. It is fabricated in a 0.8 /spl mu/m double-poly complementary bipolar process.

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology

Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of −157dBFS/Hz (i.e. DR = 60dB) while dissipating 2.9W.

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]

An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth (BW). An automatic-gain-control (AGC) loop is placed around the analog-to-digital converter (ADC). Amplitude-modulation (AM) caused by gain switching is corrected digitally.