Carsten Grass

Fluorine interface treatments within the gate stack for defect passivation in 28 nm high-k metal gate technology

A novel method of fluorine incorporation into the gate dielectric by gaseous thermal NF3 interface treatments for defect passivation have been investigated in 28 nm high-k metal gate technology with respect to improvement in device reliability. The thermal treatment suppresses physical interface regrowth observed in previous plasma-assisted fluorine treatments. Detailed defect characterization by spectroscopic charge pumping is used to characterize the influence of fluorine on trap states in the interfacial oxide layer. Comprehensive structural as well as electrical characterization linked with bias temperature instability measurements indicates the potential of improving reliability in high-k metal gate technology by gaseous introduction of fluorine into the gate dielectric.

Advanced gate stack work function optimization and substrate dependent strain interactions on HKMG first stacks for 28nm VLSI ultra low power technologies

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I_D,SAT = 870μA/μm and PFET I_D,SAT = 465μA/μm at I_OFF = 1nA/μm and V_DS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.