Jan Hoentschel

Advanced SOI CMOS transistor technologies for high-performance microprocessor applications

We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Strained Silicon Devices

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

From the present to the future: Scaling of planar VLSI-CMOS devices towards 3D-FinFETs and beyond 10nm CMOS technologies; manufacturing challenges and future technology concepts

Jan Hoentschel works for GLOBALFOUNDRIES as a Device Manager and is responsible for 28nm low power technologies. He manages an international device engineering team, which is handling several low power CMOS technologies starting from 40nm down to 28nm. Before he was working with Advanced Micro Devices and served several PD-SOI-CMOS device integrations from 130nm down to 32nm technologies for high performance microprocessors. In addition he was working within the product interaction and implementation group at AMD in Austin, TX. Jan Hoentschel is author and co-author of numerous technical papers and patents in the semiconductor field. He holds an MS and PhD in electrical engineering from the Technical University in Dresden as well as an MBA in General Management from the University of Applied Science Bielefeld. His research interests include HKMG, strain engineering, 3D FinFET device and technology concepts, lIIiV semiconductors and low power technologies on CMOS devices.

Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond

This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with 110>; channel direction. Therefore it is a simple low-cost stress method for Tri-Gate and FinFET structures of 22nm technologies and beyond. The main stress direction is located along the channel width with a maximum near the pn-junctions. The stress effect can be improved further with reduced gate length which shows the compatibility of strained isolation oxide to future transistor generations.

Advanced gate stack work function optimization and substrate dependent strain interactions on HKMG first stacks for 28nm VLSI ultra low power technologies

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I_D,SAT = 870μA/μm and PFET I_D,SAT = 465μA/μm at I_OFF = 1nA/μm and V_DS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.

Taking the next step on advanced HKMG SOI technologies — From 32nm PD SOI volume production to 28nm FD SOI and beyond

A foundrys mission is to deliver competitive device performance and flexibility to support a variety of SoC offerings. The restrictive lithography and process requirements at the 20nm technology limit harvesting the density and scaling benefits of the gate first approach and drive the concept change to gate last processing. This technology pushes conventional scaling to its challenging limits. Beyond 20nm new device concepts need to be employed where FinFETs and ET-SOI devices serving well candidates for new advanced CMOS technologies.

Advanced technology nodes, a foundry perspective

Leading edge foundries need to fulfill a wide range of customer needs and have to deliver state-of-the-art performance processes. Therefore, an innovative but flexible modular technology set up is essential. This paper will show after a brief introduction of foundry challenges in general Global Foundries path towards the 28nm technology. Here, two key elements like high k metal gate process and embedded stressors are discussed. The article is concluded with an outlook on future device scaling from a leading edge foundry’s perspective. This look ahead includes recent transistor architecture and process technology trends. More specifically, some challenges of the 20nm technology are discussed. This node will push planar transistor technology to its physical limits. Due to this, subsequent nodes will require substantial innovations in process architecture and device concepts. Two potential device paths are foreseen and compared, i.e. FinFet and ET-SOI-UTBB devices.