Carsten Wegener

Linear Model-Based Error Identification and Calibration for Data Converters

For the example of a 12-bit Nyquist-rate ADC, a model for nonlinearity-causing mechanisms is developed based on circuit simulations. The model is used to estimate circuit element values from measured device characteristics. Post-manufacture reconfiguration of the digital control part of the device-type that is used as a test vehicle in this work can improve the linearity performance of a device. An algorithm is proposed that searches for a locally-optimal reconfiguration based on the determined circuit element values. Applying calibration to the circuit simulation model allows one to estimate the performance improvement obtainable with the proposed calibration scheme for a given manufacturing process prior to a physical implementation.

Test Development Through Defect and Test Escape Level Estimation for Data Converters

Testing integrated circuits (ICs) is understood as the task of filtering out defective ICs that violate data sheet specifications. The costs of this filter comprise both the direct cost of testing a device and the indirect cost of test escapes and test yield–loss. For analog and mixed-signal devices, such as data converters, traditional methods of estimating the defect and test escape levels require large sample sets of devices. This is because the defect level induced by manufacturing process variations is typically low. In this work, a model-based method of estimating defect and test escape levels is described. For this method, a small set of sample devices is sufficient, as we first derive a manufacturing process model which is then used to simulate the manufacturing of a large number of devices. These simulation results are subsequently used for the purposes of estimating the defect and test escape levels, as well as the test-related yield–loss when applying a given test. With these estimates, the quality and indirect costs of a test can be determined as a function of the test limits and guard-bands applied in production test.

Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs

Test setup limitations, such as noise and parasitics, increasingly impede repeatable and accurate linearity measurements in high-volume production testing of high-precision data converters. Model-based testing has been shown to reduce the adverse effects of noise [14].In this work, we present two enhancements of the linear model-based approach: one is a change of the modeling strategy in order to account for measurement errors induced, for example, by parasitics associated with the device contactor, and another is a Design-for-Test feature that significantly improves the model’s ability to reduce the effect of measurement noise on the accuracy of the test outcome.

Implementation of model-based testing for medium- to high-resolution Nyquist-rate ADCs

The Linear Error Mechanism Modeling Algorithm (LEMMA has been developed with the aim of reducing test costs for DACs and ADCs, a particularly important class of mixed-signal integrated circuits. In this contribution, for the example of a 12-bit ADC, we report on the development and verification of LEMMA in an industrial production test environment. From the insight gained, we estimate the requirements and return-of-investment for higher resolution devices where traditional test techniques exhaust the time budget allowed for testing commodity parts.

Testing ADCs for static and dynamic INL—killing two birds with one stone

Abstract Traditionally, static linearity and dynamic distortion tests are performed separately for ADCs. A low-frequency sine wave is histogrammed to measure static Integral Nonlinearity (INL), and a high-frequency sine wave is sampled for FFT processing to measure dynamic distortions and dynamic range. This work describes a model-based technique to extract both static and dynamic nonlinearities from a single data record of a sampled high-frequency sine wave. This saves test time as the ADC converts fewer samples.

Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits

By their nature, mixed-signal circuits have to be tested for both structural integrity and parametric performance. For the example of data converters we review test pattern selection strategies geared towards structural and performance testing. We introduce a novel test pattern selection strategy that merges both objectives, and by that we achieve a significant reduction in the size of the set of test patterns applied on the production line.

Model-based testing of high-resolution ADCs

Testing Analog-to-Digital Converters (ADCs) involves time-consuming measurements to estimate the location and spacing between the transition levels. From these measurements the Integral and Differential Nonlinearity (INL and DNL) are determined and cross-checked against the values given on the data sheet. The histogram test, an all-codes test, is widely used in industry. In this work, we compare for high-resolution ADCs this test method with a short-codes method that is based on combining the servo-loop setup and the LEMMA modeling technique. We demonstrate how and why the latter method outperforms histogramming in terms of test time.

Incorporation of hard-fault-coverage in model-based testing of mixed-signal ICs

The application of the Linear Error Mechanism Modeling Algorithm (LEMMA) to various DAC and ADC architectures has raised the issue of including hard-fault-coverage as an integral part of the algorithm. In this work, we combine defect-oriented functionality tests and specification-oriented linearity tests of a mixed-signal IC to save test time. The key development is a novel test point selection strategy which not only optimizes the INL-prediction variance of the model, but also satisfies hard-fault-coverage constraints.

Extending the servo-loop for ADC transition level measurements under dynamic input conditions

For high-resolution Nyquist-rate ADCs, testing the linearity of the transfer characteristic at all-codes becomes very time consuming as the number of codes increases exponentially with resolution. Previously, a model-based test approach has been proposed based on measurements using a servo-loop. With the servo-loop, the ADC linearity is tested under static input conditions by measuring only a small subset of code transition levels. Adopting this short-codes approach, we propose a faster settling servo-loop implementation. We extend the servo-loop and the model-based short-codes test to linearity testing under dynamic input conditions.

Guest Editorial: Analog, Mixed-Signal and RF Testing

Analog, Mixed-Signal and Radio-Frequency circuits represent a small fraction of the total volume of semiconductor production. However, they pose very specific challenges and headaches – more often than not – to both design and test engineers. For complex systems, the costs of AMS-RF test and test development can lead to a bottleneck in industrialization of a product. This is the reason why a rather small but active community meets on a yearly basis at the International Mixed-Signal Testing Workshop (IMSTW). In 2015 the workshop was held in Paris and brought a number of interesting proposals to public discussion. As program chairs of IMSTW, we decided to invite submissions for a JETTA special issue with a call-forpapers open to contributions reaching beyond the workshop community. Therefore, some papers in this special issue are extended versions of IMSTW papers and others are new contributions. The first three papers deal with Built-in-Self Test (BiST). The paper by Renaud et al. discusses the details of a switched-capacitor ramp generator for static testing of high performance ADCs. This ramp generator is shown to test a Pipeline ADC with a reduced-code strategy that requires only 6 % of the total number of codes. The second paper, contributed by Roberts et al., presents a complete scheme of injecting and analyzing jitter in high-speed I/Os. Softwaregenerated Sigma-Delta bit-streams are stored in on-chip cycling registers and processed by amplitude-mode or timemode filters in order to provide robust stimulus. The signature extraction part of the BiST requires only a comparator and a few logic gates. Finally, Bashir et al. describe in the third paper a built-in measurement mechanism to evaluate the degradation due to injection pulling in a Digital-toFrequency Converter. In order to minimize the injection pulling effect, the authors introduce a programmable delay line in the circuit. Thus, the BiST hardware is used for both improving and testing device performance. IMSTW 2015 had significant contributions from the production test development community. The fourth paper in this special issue of JETTA, contributed by Leisenberger and Schatzberger, is a representative and develops a contact screening procedure for EEPROM memories. Due to high density requirements, single via contacts are used in memory arrays and this poses reliability issues. It is shown that high-resistive contacts are prone to lift-off failure but are not detected by conventional tests. Hence, an improved measurement procedure is proposed that exploits Design-for-Test modifications in the memory array. The third category gathers four papers that deal with reliability, diagnosis and machine-learning. The fifth paper of this special issue, by Yu et al., presents a statistical framework for fault diagnosis, which is based on a combination of tools: Extreme Learning Machine for the model and a Firefly algorithm for optimization (an evolutionary method, like particle swarm, where the random generation is replaced by a more efficient chaotic map). The sixth paper also deals with diagnosis but in a much different framework. The purpose of Oliveira and Machado da Silva is to identify hardware faults in a health monitoring system. They rely on a fuzzy logic system to devise whether abnormal sensor data * Gildas Léger leger@imse-cnm.csic.es