Gildas Leger

A tissue impedance measurement chip for myocardial ischemia detection

In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8-/spl mu/m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions.

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs

Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions.

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.

An integrated circuit for tissue impedance measure

In this paper, the design of as integrated circuit (IC) for the measurement of tissue impedance is presented. The chip is intended to be used in monitoring biomedical parameters in living bodies. Tissue impedance is one of these parameters which allows ischemia monitoring. The designed IC is used in a four-electrode based set-up in order to minimize the effect of electrode-electrolyte interface impedance. A needle shaped probe which contains the four electrodes for the impedance measurement and ICs required for excitation and measurement purpose have been designed, fabricated and tested in-vivo. The IC has been fabricated in a 0.8 /spl mu/m CMOS process, working at 3 V of power supply. Test results have shown the circuit feasibility.

Efficient selection of signatures for analog/RF alternate test

This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.

Low-Cost Digital Detection of Parametric Faults in Cascaded

The test of SigmaDelta modulators is cumbersome due to the high performance that they reach. Moreover, technology scaling trends raise serious doubts on the intradie repeatability of devices. An increase of variability will lead to an increase in parametric faults that are difficult to detect. In this paper, a design-oriented testing approach is proposed to perform a simple and low-cost detection of variations in important design variables of cascaded SigmaDelta modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test-time minimization in mind, as a function of the desired measurement precision. The developments are supported by experimental results that validate the proposal.

\Sigma\Delta

This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.

Modulators

This paper is a practical illustration of the adoption of alternate tests based upon the judicious selection of the set of parameters to be considered for design as well as to be observed subsequently. The notion of signatures is introduced, and their ability to predict design accuracy is analyzed. The application is demonstrated for an RF LNA circuit.

Sine-Wave Signal Characterization Using Square-Wave and ΣΔ-Modulation: Application to Mixed-Signal BIST

This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analogue sine-wave signal. The required circuitry for on-chip implementation is very simple and robust, which makes the present approach very suitable for BIST applications. Solutions in this sense are addressed together with simulation results that validate the feasibility of the proposed approach.

A Procedure for Alternate Test Feature Design and Selection

This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.