Catherine Dezan

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids

Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated. Most conventional defect/fault-tolerance techniques are not suitable in nanoscale designs because they are designed for very small defect rates and assume arbitrary layouts for required circuits. Reconfigurable approaches face fundamental challenges including a complex interface between the micro and nano components required for programming. In this paper, we present our work on adding fault-tolerance to all components of a processor implemented on a 2-D semiconductor NW fabric called nanoscale application specific integrated circuits (NASICs). We combine and explore structural redundancy, built-in nanoscale error correcting circuitry, and system-level redundancy techniques and adapt the techniques to the NASIC fabric. Faulty signals caused by defects and other error sources are masked on-the-fly at various levels of granularity. Faults can be masked at up to 15% rates, while maintaining a 7 density advantage compared to an equivalent CMOS processor at projected 18-nm technology. Detailed analysis of yield, density, and area tradeoffs is provided for different error sources and fault distributions.

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.

Regular 2D NASIC-based architecture and design space exploration

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

FPGA implementation of Bayesian network inference for an embedded diagnosis

Critical systems, like Unmanned Aerial Systems (UAS) operate in uncertain environments and have to face unexpected obstacles, weather changes and sensor, hardware or software failures. Therefore, a health management system is needed to detect and locate the failure in real time. In this paper, we propose a Field Programmable Gate Array (FPGA) implementation based on a Bayesian network (BN) representation, that allows to continuously monitor the embedded system under time and resource constraints. The hardware implementation is generated by a specific off-line framework integrating a high-level synthesis tool. The proposal is evaluated on a hybrid reconfigurable device to show potential speed-up. Some variations on the hardware implementation are also explored to give the best trade-off between accuracy, performance and resource allocation.

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA

On the case study of block turbo decoders for error correction, the paper shows that the use of unconventional framework like Madeo can produce interesting FPGA implementations. Error correction algorithms are known to be very important for communication data rate and reliability. As reconfigurable architectures are attractive for fast prototyping and flexibility, they are often considered as support for implementation of communication, including mobile communication. Madeo is an open framework for designing physical FPGA architectures and their applications. On the basis of an abstract model for reconfigurable circuits, Madeo provides the necessary tools (logic synthesis and physical tool) to program them. The paper describes the block turbo decoder principle, discusses existing solutions and presents characteristics of a partial implementation on the open framework Madeo. Three elements of a block turbo decoder have been designed using Madeo and the physical solutions compete very well with existing solutions for such problems.

Bayesian network-based framework for the design of reconfigurable health management monitors

Modern small-size UAVs depend on highly complex architectures with many sensors and computer-controlled actuators. The size, weight and budget constraints leave little or no room for redundant systems. So all components must be reliable and any fault must be detected as early as possible. In this paper, we propose an adaptive, real-time, on-board system to continuously monitor sensors, software, and hardware components for the detection and diagnosis of failures by means of Bayesian networks. In particular, we propose an optimized hardware implementation of Bayesian Networks (BNs) for monitoring and exploiting the evidence. We consider FPGA for both performances and the ability to dynamically configure the hardware according to mission applications. Finally, we introduce an off-line framework that can generate FPGA implementations of the monitors for embedded systems under time and resource constraints.

Fine grain parallel decoding of turbo product codes: Algorithm and architecture

In turbo decoding of product codes, we propose an algorithm implementation, based on the Chase-Pyndiah algorithm, which exhibits a modular, simple structure with fine grain parallelism. It is implemented into deep pipelined architectures, including an interleaving block decoding scheme, with good potential on FPGAs and MP-SoCs targets. We include an evaluation of the essential parameters of those architectures, which are situated in a different area of the block turbo decoder implementation design space.

Embedded Context Aware Diagnosis for a UAV SoC platform

Abstract Autonomous Unmanned Aerial Vehicles (UAVs) operate under uncertain environmental conditions and can have to face unexpected obstacles, weather changes and sensor or hardware/software component failures. In such situations, the UAV must be able to detect and locate the failure and to take adequate recovery actions. In this paper, we focus on the Health Management of the system depending on the context of the mission. The task of this Health Management is to monitor the status of the system components based on observations from sensors and appearance contexts, and it is designed by means of Bayesian Networks arising from the Failure Mode and Effects Analysis. We jointly introduce a framework to generate embedded software and hardware implementations for online and real-time observations, which are demonstrated on a Hybrid CPU/FPGA Zynq platform.

Embedded real-time localization of UAV based on an hybrid device

This paper presents a method for localizing an Unmanned Aerial Vehicle (UAV) in indoor or outdoor environments. The approach has the ability to estimate the 3D pose of the on-board camera by using a Harris corner detector and the Levenberg-Marquardt (LM) with the Random Sample Consensus (RANSAC) algorithm to perform detection. The implementation of such computational intensive tasks in embedded system is necessary for the autonomy of UAV. Accelerators implemented on FPGA provide a solution to reach required performances. In addition to the algorithm development, we present the embedding of a real time camera pose estimation algorithm on a Xilinx System on Programmable Chip (SoPC) platform. Partitioning of our embedded application into hardware and software parts on a Zynq Board has significantly reduced the execution time when compared with software implementation, while offering necessary reconfiguration capabilities.

Embedded and probabilistic health management for the GPS of autonomous vehicles

The aim of this paper is to propose a complementary Health Management module to monitor the GPS accuracy for autonomous vehicles. Based on sensor information, the error causes of GPS can be observed in some specific contexts (urban, climate...). The proposed module relies on a Bayesian Network model that allows to reinforce the belief of GPS failure based on evidence. A hardware/software implementation of the Health Management module is also proposed for real-time and on-line purposes on an embedded platform.