Loïc Lagadec

A Design Approach to Automatically Synthesize ANSI-C Assertions during High-Level Synthesis of Hardware Accelerators

Evolution of Systems-On-Chip (SoC) increases the challenge of verification and post-silicon debug. Nowadays, Assertion Based Verification (ABV) is a widely used methodology. Languages like PSL (Property Specification Language) or SVA (System Verilog Assertions) allows engineers to define properties at Register Transfer Level (RTL). Properties can then be used to generate simulation/hardware assertion checkers for dynamic verification. In this paper, we propose to consider ANSI-C assertions during High-Level Synthesis (HLS) of hardware accelerators (HWacc) to automatically generate on-chip monitors (OCM). The proposed method is portable to any HLS tool and supports both static and dynamic application behaviors. OCM is implemented separately from the HWacc and an original technique is introduced for their synchronization. Two synthesis options are proposed for the OCM design i.e. speed and area. Experimental results show the interest of the proposed approach: while the cost of the OCMs mainly depends on the complexity of input assertions, setting synthesis option is area allows reducing the complexity of the OCM by 2.37x on average compared to the option for speed optimization.

Object oriented meta tools for reconfigurable architectures

A number of experimental and commercial reconfigurable architectures are designed with various objectives: random logic integration, hardware prototyping, computation accelerators, planar smart sensors or transducers etc Getting a new reconfigurable part to the final user remains a very difficult task, because there are no common tools, nor are there standard models that provides retargeting software development tools. A generic model for reconfigurable circuits has been built in three stages: full implementation of tools for a practical platform, creation of an abstract model and associated tools for arbitrary architectures ( programmable editor, geometric operations on physical modules, place and route), description tools for concrete architecture defined as a specialization of the abstract model. Main advantages and further fields of research based on this approach are: retargetable tools based on a description of the new architecture with possibility to embed new primitives, possibility of a quantitative approach in the design of new reconfigurable architectures.

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.

Regular 2D NASIC-based architecture and design space exploration

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

Smalltalk debug lives in the matrix

Agile programming aware computer scientists know how much productivity they owe to their development environments, and more precisely to advanced debuggers. Indeed, debuggers are mandatory to support an optimistic do-fix-rerun approach. This development scheme does not make sense in hardware design where agile has a different meaning; it refers to reconfigurable architectures. Despite such architectures support tailoring and refactoring application circuits and promote short development cycles, the overall programing scheme still conforms to waterfall models and component based integration. This paper presents a path to offer probe-based development to hardware designers, and introduces our Red Pill environment that merges several abstraction levels ranging from C like parallel coding to hardware realization embedding debug facility. Red Pill is developed using VisualWorks and reproduces some of Cincom Smalltalk browser well known features that traditionally lack when validating circuits.

Toolset for nano-reconfigurable computing

Contrasting with the extensive research focusing on nano-devices properties and fabrication, not enough attention is probably given to computing architectures for these devices. This paper describes a method for mapping an FPGA architecture to a nano-device called NASIC (for Nano-ASIC). This mapping is an illustration of the interest of nano- and micro-architecture models stacked to quickly obtain CAD environments for the investigated technologies.

Model-driven toolset for embedded reconfigurable cores

Improvements in system cost, size, performance, power dissipation, and design turnaround time are the key benefits offered by System-on-Chip designs. However they come at the cost of an increased complexity and long development cycles. Integrating reconfigurable cores offers a way to increase their flexibility and lifespan. However the integration of embedded reconfigurable units poses a number of unique challenges in terms of design-space exploration and system exploitation. Over the last few years, model-driven engineering has become one of the most promising methodologies for tackling such challenging software problems.This paper presents Biniou, a model-driven toolset for embedded reconfigurable core modeling. Biniou is a major step ahead of the Madeo framework that was one of the rare non-commercial environments targeting reconfigurable design automation. In Biniou, the design space is broadened with (re-)configuration modeling aspects, and the exploitation tools are enhanced through the use of multi-level simulation and high-level debugging.These advancements are illustrated through a case-study focused on the design-space exploration of a coarse-grained reconfigurable architecture and through an examination of the integration of the debug-specific features into the framework. The main benefits of the presented toolset are: efficient domain-space exploration (validation), software design-kit generation (usability), software-like debug facilities (verification). We model embedded reconfigurable cores.We consider modeling the configuration plane.We generate a fully-featured prototype.We offer an object-oriented view of the prototype.We support high-level debugging through observability, traceability and controllability.

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA

On the case study of block turbo decoders for error correction, the paper shows that the use of unconventional framework like Madeo can produce interesting FPGA implementations. Error correction algorithms are known to be very important for communication data rate and reliability. As reconfigurable architectures are attractive for fast prototyping and flexibility, they are often considered as support for implementation of communication, including mobile communication. Madeo is an open framework for designing physical FPGA architectures and their applications. On the basis of an abstract model for reconfigurable circuits, Madeo provides the necessary tools (logic synthesis and physical tool) to program them. The paper describes the block turbo decoder principle, discusses existing solutions and presents characteristics of a partial implementation on the open framework Madeo. Three elements of a block turbo decoder have been designed using Madeo and the physical solutions compete very well with existing solutions for such problems.

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator

Embedded systems often implement safety critical applications making security a more and more important aspect in their design. Control-Flow Integrity (CFI) attacks are used to modify program behavior and can lead to learn valuable information directly or indirectly by perturbing a system and creating failures. Although CFI attacks are well-known in computer systems, they have been recently shown to be practical and feasible on embedded systems as well. In this context, CFI checks are mainly used to detect unintended software behaviors while very few works address non programmable hardware component monitoring. In this paper, we present a hardware-assisted paradigm to enhance embedded system security by detecting and preventing unintended hardware behavior. We propose a design approach that designs on-chip monitors (OCM) during High-Level Synthesis (HLS) of hardware accelerators (HWacc). Synthesis of OCM is introduced as a set of steps realized concurrently to the HLS flow of HWacc. Automatically generated OCM checks at runtime both the input/output timing behavior and the control flow of the monitored HWacc. Experimental results show the interest of the proposed approach: the error coverage on the control flow ranges from 99.75% to 100% while in average the OCM area overhead is less than 10%, the clock period overhead is at worst less than 5% and impact on the synthesis time is negligible.

Model-driven physical-design automation for FPGAs: fast prototyping and legacy reuse

The current integrated circuit technologies are approaching their physical limits in terms of scaling and power consumption, in this context, the electronic design automation (EDA) industry is pushed towards solving ever more challenging problems in terms of performance, scalability and adaptability. Meeting these constraints needs innovation at both the algorithmic and the methodological level. Amongst academic EDA tools, Madeo toolkit has been targeting field‐programmable gate array (FPGA) design‐automation at the logic and the physical level since the late 1990s. As many other long‐living software, despite embedding valuable legacy, Madeo exhibits unwanted characteristics that penalize evolution and render the automation problems even more difficult. This study presents a methodological approach to physical‐design automation relying on model‐driven engineering, which is illustrated through the incremental redesign of the Madeo framework. A benefit of this approach is the emergence of a common vocabulary to describe the EDA domain in an FPGA scope. A second advantage is the isolation of the optimization algorithms from the structural domain models. However, the main asset is the possibility to re‐inject into the newly designed toolkit most of the legacy code. The redesigned framework is compared with and scored against initial code‐base, and demonstrates a regression‐free remodeling of the environment with net improvements in terms of size and complexity metrics. As a consequence, the evolution capability is back on stage, and the domain‐space exploration widens to the algorithmic axis. Copyright