Cedric Monget

Etch challenges for DSA implementation in CMOS via patterning

This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer’s Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti’s 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

Copper-Line Topology Impact on the Reliability of SiOCH Low-

SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub-45-nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With line-to-line spacing reduction, the control of the line shape and of the spacing uniformity within a wafer is becoming first-order parameters governing the low- k dielectric reliability. Improving the low- k reliability requires to discriminate each topological effect and to quantify its impact on the lifetime at product level. This paper demonstrates that the copper line shape induces a preferential breakdown of the dielectric close to the SiOCH/SiCN capping even at nominal voltage. The impact of the line edge roughness is studied with the introduction of a simple analytical model. Moreover, the impact of the roughness on the product lifetime has been quantified. It is demonstrated that the line-to-line spacing variation is less critical at the operational voltage than at high voltage stress. Finally, the impact of the spacing uniformity within the wafer and from wafer to wafer (reflecting the spacing fluctuation from product to product) on the Weibull shape is quantified and reported to be voltage-dependent in agreement with the experimental detail.

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Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising solutions for sub-10 nm nodes. However, some challenges need to be addressed for a complete adoption of DSA in manufacturing such as achieving DSA-friendly design, low defectivity and accurate pattern placement. In this paper, we propose to discuss the DSA integration flows using graphoepitaxy for contact-hole patterning application. DSA process dependence on guiding pattern density has been studied and solved thanks to a new approach called “DSA planarization”. The capabilities of this new approach have been evaluated in terms of defectivity, Critical Dimension (CD) control and uniformity before and after DSA etching transfer.

for the 45-nm Technology Node and Beyond

SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.

DSA planarization approach to solve pattern density issue

Abstract. Directed self-assembly (DSA) of block copolymers has shown interesting results for contact hole application, as a vertical interconnection access for CMOS sub-10 nm technology. The control of critical dimension uniformity (CDU), defectivity, and placement error (PE) is challenging and depends on multiple processes and material parameters. This paper reports the work done using the 300-mm pilot line available in materials to integrate the DSA process on contact and via level patterning. In the first part, a reliable methodology for PE measurement is defined. By tuning intrinsic edge detection parameters on standard reference images, the working window is determined. The methodology is then implemented to analyze the experimental data. The impact of the planarization process on PE and the importance of PE as a complement of CDU and hole open yield for process window determination are discussed.

Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime

Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.

Placement error in directed self-assembly of block copolymers for contact hole application

DSA patterning is a promising solution for advanced lithography as a complementary technique to standard and future lithographic technologies. In this work, we focused on DSA grapho-epitaxy process-flow dedicated for contact hole applications using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers. We investigated the impact on the DSA performances of the surface affinity of a guiding pattern design by ArF immersion lithography. The objective was to control and reduce the polymer residue at the bottom of the guiding pattern cavities since it can lead to lower a DSA-related defectivity after subsequent transfer of the DSA pattern. For this purpose, the DSA performances were evaluated as a function of the template surface affinity properties. The surface affinities were customized to enhance DSA performances for a PS-b-PMMA block copolymer (intrinsic period 35nm, cylindrical morphology) by monitoring three main key parameters: the hole open yield (HOY), the critical dimension uniformity (CDU-3σ) and the placement error (PE-3σ). Scanning transmission electron microscopy (STEM) was conjointly carried out on the optimized wafers to characterize the residual polymer thickness after PMMA removal. The best DSA process performances (i.e., hole open yield: 100%, CDU-3σ: 1.3nm and PE-3σ: 1.3nm) were achieved with a thickness polymer residue of 7 nm. In addition, the DSA-related defectivity investigation performed by review-SEM enabled us to achieve a dense (pitch 120nm) contact area superior to 0.01mm2 free of DSA-related defects. This result represents more than 6x105 SEM-inspected valid contacts, attesting the progress achieved over the last years and witnessing the maturity of the DSA in the case of contact holes shrink application.

Template affinity role in CH shrink by DSA planarization

In this paper, we focus on the directed-self-assembly (DSA) application for contact hole (CH) patterning using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers (BCPs). By employing the DSA planarization process, we highlight the DSA advantages for CH shrink, repair and multiplication which are extremely needed to push forward the limits of currently used lithography. Meanwhile, we overcome the issue of pattern densityrelated- defects that are encountered with the commonly-used graphoepitaxy process flow. Our study also aims to evaluate DSA performances as function of material properties and process conditions by monitoring main key manufacturing process parameters: CD uniformity (CDU), placement error (PE) and defectivity (Hole Open Yield = HOY). Concerning process, it is shown that the control of surface affinity and the optimization of self-assembly annealing conditions enable to significantly enhance CDU and PE. Regarding materials properties, we show that the best BCP composition for CH patterning should be set at 70/30 of PS/PMMA total weight ratio. Moreover, it is found that increasing the PS homopolymer content from 0.2% to 1% has no impact on DSA performances. Using a C35 BCP (cylinder-forming BCP of natural period L0 = 35nm), high DSA performances are achieved: CDU-3σ = 1.2nm, PE-3σ = 1.2nm and HOY = 100%. The stability of DSA process is also demonstrated through the process follow-up on both patterned and unpatterned surfaces over several weeks. Finally, simulation results, using a phase field model based on Ohta-Kawasaki energy functional are presented and discussed with regards to experiments.

Advanced surface affinity control for DSA contact hole shrink applications

Directed Self-Assembly (DSA) is a well-known candidate for next generation sub-15nm half-pitch lithography. [1-2] DSA processes on 300mm wafers have been demonstrated for several years, and have given a strong impression due to finer pattern results. [3-4] On t he other hand, specific issues with DSA processes have begun to be clear as a result of these recent challenges. [5-6] Pattern placement error, which means the pattern shift after DSA fabrication, is recognized as one of these typical issues. Coat-Develop Track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performance.[4] In this study, the placement error was investigated using a simple contact-hole pattern and subsequent contact-hole shrink process implemented on the SOKUDO DUO track. Thus, we will show the placement error of contact-hole shrink using a DSA process and discuss the difference between DSA and other shrink methods.

Process highlights to enhance DSA contact patterning performances

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.