Celina Gazda

A Wideband Common-Mode Suppression Filter for Bend Discontinuities in Differential Signaling Using Tightly Coupled Microstrips

A new type of bend is proposed that reduces differential-to-common mode conversion occuring at the bend discontinuity in coupled microstrip lines for high-speed digital circuits. Simultaneously, great care has been taken to minimize the differential reflection coefficient and insertion loss, leading to an overall improved signal integrity. This is achieved by tapering the microstrip lines to tightly or very tightly coupled ones in the area of the bend. Full-wave simulations in the DC to 6 GHz frequency range show that over 9 dB and 14 dB suppression of conversion noise is achieved for tightly coupled and very tightly coupled bends, respectively. Also for these new structures, with a total length of 100 mm, the insertion loss remains below 0.6 dB. Measurements on prototype bends show very good agreement with full-wave simulations. Also time domain measurements demonstrate the significant reduction in conversion noise while keeping return loss low. Moreover, for design purposes, a dedicated circuit model which closely matches the full-wave characteristics of the proposed bends is presented.

Harmonic Balance Surrogate-Based Immunity Modeling of a Nonlinear Analog Circuit

A novel harmonic balance surrogate-based technique to create fast and accurate behavioral models predicting, in the early design stage, the performance of nonlinear analog devices during immunity tests is presented. The obtained immunity model hides the real netlist, reduces the simulation time, and avoids expensive and time-consuming measurements after tape-out, while still providing high accuracy. The model can easily be integrated into a circuit simulator together with additional subcircuits, e.g., board and package models, as such allowing to efficiently reproduce complete immunity test setups during the early design stage and without disclosing any intellectual property. The novel method is validated by means of application to an industrial case study, being an automotive voltage regulator, clearly showing the techniques capabilities and practical advantages.

Constrained Multiobjective Optimization of a Common-Mode Suppression Filter

Designing an optimized common-mode suppression filter for a bend in a differential trace pair on a printed circuit board involves determining the geometrical parameters that simultaneously provide a large reduction of conversion noise, a small differential mode reflection coefficient and low overall loss, given hardware and manufacturing constraints. Therefore, a novel constrained multiobjective optimization technique is proposed that relies on intermediate surrogate models of the different cost functions instead of numerically expensive full-wave simulations, saving CPU time and memory resources. As a result, a 3-D Pareto-front is created and then constrained based on hardware limitations, depicting the tradeoff between the costs and allowing an easy selection of the most optimal layout geometry.

Time domain analysis of a wideband common-mode suppression filter for bent interconnects

A technique to efficiently reduce differential-to-common mode conversion occuring at a bend discontinuity in coupled microstrip lines is investigated. Total signal integrity in the interconnect structure has been improved by minimizing the differential reflection coefficient and insertion loss simultaneously. This is achieved by changing the geometry of the microstrip lines via a tapering section to tightly or very tightly coupled ones in the area of the bend. The new design was manufactured, measured, and validated by means of time-domain analysis, providing very satisfactory results.

Efficient Circuit Modeling Technique for the Analysis and Optimization of ISO 10605 Field Coupled Electrostatic Discharge (ESD) Robustness of Nonlinear Devices

In this paper, we propose a circuit modeling technique for the ISO 10605 field-coupled electrostatic discharge (ESD) test, often used in the automotive sector. First, a novel circuit model of the ESD gun is proposed. Second, a circuit model is developed for the ISO 10605 field-coupled ESD test bench and concatenated with models for the load box and the device under test (DUT). To validate the advocated models, a nonlinear DUT is simulated, manufactured, and measured under the ISO 10605 field-coupled ESD test conditions. Furthermore, it is shown that the circuit model can be used to efficiently optimize the design of the DUT, making it more robust against ESD disturbances. The optimized DUT design was again manufactured and measured, validating the simulated results.

A black-box measurement-based modeling method for the RF emission and immunity behavior of ICs

A method is proposed that allows to construct behavioral models of the radio frequency (RF) emission and immunity performance of an integrated circuit (IC) without requiring any knowledge of its internal architecture or activity. It is based on three types of measurements: (1) multi-port scattering parameter (S-parameter) measurements using a vector network analyzer, (2) conducted emission measurements using an electromagnetic interference (EMI) receiver, and (3) conducted immunity measurements using a Direct Power Injection (DPI) test set-up. For these measurements, the IC-to-be-modeled is mounted on a simple test board that only contains 50-Ω microstrip lines running to each pin that needs to be included in the model. No other connections to the IC are provided on this board as all connections are made externally by means of properly selected commercial off-the-shelf (COTS) bias tees. In this way, it is made sure that the models only cover the intrinsic performance of the IC itself and that their validity is not limited to a particular application board or circuit environment. In this paper, the method is applied to a standard position sensor IC in the frequency range of 300 kHz to 2.5 GHz. However, the method should work well from nearly DC to about 3 GHz for ICs with (1) package dimensions of less than 10 mm × 10 mm × 2.5 mm, and (2) less than 12 pins to be included in the model.