Cesar Torres-Huitzil

FPGA-based configurable systolic architecture for window-based image processing

Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of GOPs at a 60 MHz clock frequency and a processing time of milliseconds for generic window-based operators on gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.

An FPGA architecture for high speed edge and corner detection

This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.

Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation

Despite several previous studies, little progress has been made in building successful neural systems for image segmentation in digital hardware. Spiking neural networks offer an opportunity to develop models of visual perception without any complex structure based on multiple neural maps. Such models use elementary asynchronous computations that have motivated several implementations on analog devices, whereas digital implementations appear as quite unable to handle large spiking neural networks, for lack of density. Recent results show that this trend is now counterbalanced by FPGA technological improvements and new implementation schemes. In this work, we consider a model of integrate-and-fire neurons organized according to the standard LEGION architecture to segment gray-level images. Taking advantage of the local and distributed structure of the model, a massively distributed implementation on FPGA using pipelined serial computations is developed. Results show that digital and flexible solutions may efficiently handle large networks of spiking neurons.

2013 Special Issue: FPGA implementation of a configurable neuromorphic CPG-based locomotion controller

Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion.

A CPG system based on spiking neurons for hexapod robot locomotion

In this paper, we propose a locomotion system based on a central pattern generator (CPG) for a hexapod robot, suitable for embedded hardware implementation. The CPG system was built as a network of spiking neurons, which produce rhythmic signals for three different gaits (walk, jogging and run) in the hexapod robot. The spiking neuron model used in this work is a simplified form of the well-known generalized Integrate-and-Fire neuron model, which can be trained using the Simplex method. The use of spiking neurons makes the system highly suitable for digital hardware implementations that exploit the inherent parallelism to replicate the intrinsic, computationally efficient, distributed control mechanism of CPGs. The system has been implemented on a Spartan 6 FPGA board and fully validated on a hexapod robot. Experimental results show the effectiveness of the proposed approach, based on existing models and techniques, for hexapod rhythmic locomotion.

Real-time field programmable gate array architecture for computer vision

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to mini- mize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to im- prove its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very-large-scale-integrated de- vices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Hardware/software codesign for embedded implementation of neural networks

The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.

Hardware implementation of a CPG-based locomotion control for quadruped robots

This paper presents a hardware implementation of a controller to generate adaptive gait patterns for quadruped robots inspired by biological Central Pattern Generators (CPGs). The basic CPGs are modeled as non-linear oscillators which are connected one to each other through coupling parameters that can be modified for different gaits. The proposed implementation is based on an specific digital module for CPGs attached to a soft-core processor so as to provide an integrated and flexible embedded system. The system is implemented on a Field Programmable Gate Array (FPGA) device providing a compact and low power consumption solution for generating periodic rhythmic patterns in robot control applications. Experimental results show that the proposed implementation is able to generate suitable gait patterns, such as walking, trotting, and galloping.

Design and Implementation of a CFAR Processor for Target Detection

Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.

Mobile phone middleware architecture for energy and context awareness in location-based services.

The disruptive innovation of smartphone technology has enabled the development of mobile sensing applications leveraged on specialized sensors embedded in the device. These novel mobile phone applications rely on advanced sensor information processes, which mainly involve raw data acquisition, feature extraction, data interpretation and transmission. However, the continuous accessing of sensing resources to acquire sensor data in smartphones is still very expensive in terms of energy, particularly due to the periodic use of power-intensive sensors, such as the Global Positioning System (GPS) receiver. The key underlying idea to design energy-efficient schemes is to control the duty cycle of the GPS receiver. However, adapting the sensing rate based on dynamic context changes through a flexible middleware has received little attention in the literature. In this paper, we propose a novel modular middleware architecture and runtime environment to directly interface with application programming interfaces (APIs) and embedded sensors in order to manage the duty cycle process based on energy and context aspects. The proposed solution has been implemented in the Android software stack. It allows continuous location tracking in a timely manner and in a transparent way to the user. It also enables the deployment of sensing policies to appropriately control the sampling rate based on both energy and perceived context. We validate the proposed solution taking into account a reference location-based service (LBS) architecture. A cloud-based storage service along with online mobility analysis tools have been used to store and access sensed data. Experimental measurements demonstrate the feasibility and efficiency of our middleware, in terms of energy and location resolution.