René Cumplido

An FPGA-based parallel sorting architecture for the Burrows Wheeler transform

Burrows-Wheeler transform (BWT) has received special attention due to its effectiveness in lossless data compression algorithms. However, implementations of BWT-based algorithms have been limited due to the complexity of the suffix sorting process applied to the input string. Proposed solutions involve data structures combined with hardware architectures aimed at reducing computational complexity. However, advanced data structures are difficult to be implemented directly into hardware architectures as they require sophisticated control units. In this paper we present a novel architecture based on a parallel sorting block to implement the BWT transform. The proposed architecture has been implemented on a field programmable gate array (FPGA) device providing good performance improvements compared with other reported implementations on FPGAs. Results obtained show a reduction in the number of cycles and an increase in the maximum frequency compared with other works. FPGA implementation results are presented and discussed.

Decision Tree Based FPGA-Architecture for Texture Sea State Classification

The target detection process in sea clutter background involves the use of different types of CFAR (constant false alarm rate) algorithms. These algorithms and their parameters should be configured to obtain the maximum detection probability and minimum false alarm probability at the current sea state (Beaufort scale). This paper present an FPGA-architecture for automatic classification based on texture recognition of sea states. The sea state texture classification allows select the appropriate CFAR algorithm and its parameters for the target detection process. The paper is centered in the hardware implementation for sea state texture classification, based on decision tree. The rules for decision tree are obtained from the analysis of the grey levels co-occurrence matrix features applied in an image of the sea state obtained in a radar scan. Results with simulated and real data are presented and discussed

FPGA Hardware Architecture of the Steganographic ConText Technique

This work presents a hardware architecture of the ConText steganographic technique in a Cyclone II FPGA of the Altera family. The ConText technique takes advantage of noisy regions and those with abrupt gray levels changes in an image where the hidden information is very difficult to detect; the process to locate this region is highly repetitive and computationally expensive. The technique is implemented in an FPGA to increase the processing speed. The implementation results show a throughput of 61.5 Mbps.

Design and implementation of an FPGA-Based 1.452-gbps non-pipelined AES architecture

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).

A reconfigurable GF(2 M ) elliptic curve cryptographic coprocessor

Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.

Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard

Applications of wireless communications networks are emerging continuously. To offer a good level of security in these applications, new standards for wireless communications propose solutions based on cryptographic algorithms working on special modes of operation. This work presents a custom hardware architecture for the AES-CCM protocol (AES-CCMP) which is the basis for the security architecture of the IEEE 802.11i standard. AES-CCMP is based on the AES-CCM algorithm that performs the Advanced Encryption Standard (AES) in CTR with CBC-MAC mode (CCM mode), plus specialized data formatting modules, providing different security services through iterative and complex operations. Results of implementing the proposed architecture targeting FPGA devices are presented and discussed. A comparison against similar works shows significant improvements in terms of both throughput and efficiency.

On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004

Current and future communication schemes tend to use OFDM systems in order to provide high baud rates and less inter symbol interference. Some examples are 802.11, 802.16, MC-CDMA, Digital Video Broadcasting, Wireless USB and Wireless Firewire. Trying to provide a solution to the new emerging devices, slow standard adoption and poor spectrum use, Joe Mitola introduced the concept of Software Defined Radio (SDR), which involves exhaustive configurable digital signal processing like FFT. This work presents the design, validation and FPGA based implementation of an Orthogonal Frequency Division Multiplexing (OFDM) modulator for IEEE 802.16 using a high level design tool, and also reports the resources requirements for the presented system.

Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR

Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GF(2^m), is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. FPGAs allow the implementation of this kind of algorithms in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for constructing GF(2^m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) and study their area-performance trade-offs. Different Montgomery multipliers were implemented using several digits and finite fields to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to show suitable configurations for ECC implementations using NIST recommended parameters. The results achieved show a notable improvement against FPGA Montgomery multiplier previously reported, achieving the highest throughput and the best efficiency.

An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography

A hardware architecture for GF(2^m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.

FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks

Reconfigurable architectures are important elements on the design of software radios. Nowadays, diverse platforms are being developed to support multiple tasks; these platforms are designed specially for the different layers of the OSI (Open System Interconnection) reference model. Specifically, the security architectures described in the MAC sublayer should be evaluated, which are based on cryptographic algorithms that require high computational costs. In this work, two proposed AES-CCM hardware architectures for the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards are implemented in diverse FPGA devices to examine implementation costs and performance evaluation. The results presented in this work will be used for designing and developing a reconfigurable platform with software-radio applications, which will include the high-performance AES-CCM hardware architectures meeting the specifications of the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards.