Chan-Yong Jeong

Investigation of the charge transport mechanism and subgap density of states in p-type Cu2O thin-film transistors

We investigate the charge transport mechanism and subgap density of states (DOS) in p-type Cu2O thin-film transistors (TFTs) using the bias and temperature dependence of the drain currents. Among several charge transport mechanisms, the experimental data are well matched with a multiple trapping and release model, which suggests that the charge transport in the Cu2O TFT is mainly limited by trap states at grain boundaries or dielectric/semiconductor interface. The subgap DOS is extracted based on the Meyer-Neldel rule. Large density of subgap states is extracted, which is considered to be the reason of low mobility in fabricated Cu2O TFTs.

Environment-Dependent Bias Stress Stability of P-Type SnO Thin-Film Transistors

We investigate the effects of environmental water and oxygen on the electrical stability of p-type tin monoxide (SnO) thin-film transistors (TFTs). Under negative gate bias stresses, there was a larger threshold voltage shift (ΔVth) in the devices that had been exposed to water than that for the devices that remained unexposed. However, under positive gate bias stresses, devices that had been exposed to water exhibited approximately the same ΔVth as what was observed in devices that had not been exposed. This phenomenon is attributed to the generation of residual-water-related hole traps near the valence band edge in SnO TFTs. In addition, we observed that the environmental oxygen partial pressure had very little effect on the electrical stability of p-type SnO TFTs under either negative or positive gate bias stresses. The weak chemisorption of oxygen molecules caused by high ionization energy can be a plausible mechanism for the oxygen insensitivity of negative gate bias-stress-induced instabilities, and the low electron concentration near the exposed back-channel of p-type SnO TFTs can possible explain the oxygen insensitivity of positive gate bias-stress-induced instabilities.

Water-Mediated Photochemical Treatments for Low-Temperature Passivation of Metal-Oxide Thin-Film Transistors

The low-temperature electrical passivation of an amorphous oxide semiconductor (AOS) thin-film transistor (TFT) is achieved by a deep ultraviolet (DUV) light irradiation-water treatment-DUV irradiation (DWD) method. The water treatment of the first DUV-annealed amorphous indium-gallium-zinc-oxide (a-IGZO) thin film is likely to induce the preferred adsorption of water molecules at the oxygen vacancies and leads to subsequent hydroxide formation in the bulk a-IGZO films. Although the water treatment initially degraded the electrical performance of the a-IGZO TFTs, the second DUV irradiation on the water-treated devices may enable a more complete metal-oxygen-metal lattice formation while maintaining low oxygen vacancies in the oxide films. Overall, the stable and dense metal-oxygen-metal (M-O-M) network formation could be easily achieved at low temperatures (below 150 °C). The successful passivation of structural imperfections in the a-IGZO TFTs, such as hydroxyl group (OH-) and oxygen vacancies, mainly results in the enhanced electrical performances of the DWD-processed a-IGZO TFTs (on/off current ratio of 8.65 × 10(9), subthreshold slope of 0.16 V/decade, an average mobility of >6.94 cm(2) V(-1) s(-1), and a bias stability of ΔVTH < 2.5 V), which show more than a 30% improvement over the simple DUV-treated a-IGZO TFTs.

A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization

We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and drain bias stresses, and the damaged location is not limited to the drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and drain bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and drain bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and drain bias stresses in a-IGZO TFTs.

Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and drain bias stress is investigated. The stress tests under various combinations of bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect.

Fabrication of amorphous InGaZnO thin-film transistor-driven flexible thermal and pressure sensors

In this work, we present the results concerning the use of amorphous indium‐ gallium‐zinc‐oxide (a-IGZO) thin-film transistor (TFT) as a driving transistor of the flexible thermal and pressure sensors which are applicable to artificial skin systems. Although the a-IGZO TFT has been attracting much attention as a driving transistor of the next-generation flat panel displays, no study has been performed about the application of this new device to the driving transistor of the flexible sensors yet. The proposed thermal sensor pixel is composed of the series-connected a-IGZO TFT and ZnO-based thermistor fabricated on a polished metal foil, and the ZnO-based thermistor is replaced by the pressure sensitive rubber in the pressure sensor pixel. In both sensor pixels, the a-IGZO TFT acts as the driving transistor and the temperature/pressure-dependent resistance of the ZnO-based thermistor/pressure-sensitive rubber mainly determines the magnitude of the output currents. The fabricated a-IGZO TFT-driven flexible thermal sensor shows around a seven times increase in the output current as the temperature increases from 20 ◦ C to 100 ◦ C, and the a-IGZO TFT-driven flexible pressure sensors also exhibit high sensitivity under various pressure environments. (Some figures may appear in colour only in the online journal)

Effects of Post-Deposition Thermal Annealing Temperature on Electrical Properties of ZnON Thin-Film Transistors

We investigate the effects of the post-deposition thermal annealing temperature on the physical and chemical structure of zinc oxynitride (ZnON) thin films and on the electrical performance of ZnON thin-film transistors (TFTs). When a ZnON TFT is annealed at 150 °C, it exhibits conductive behavior, which is attributed to the increased electron concentration caused by the increase in the nitrogen vacancies of the defective ZnXNY bonds within the ZnON. The TFT shows the best electrical performance when the annealing temperature is 250 °C, but a degradation in the electrical performance is observed when the annealing temperature is increased to 350 °C. The significantly reduced electron concentration and the relative increase in the oxygen within the ZnON are considered as the possible reasons for the degradation in the electrical performance observed in the ZnON TFTs annealed at 350 °C.

Subgap states in p-channel tin monoxide thin-film transistors from temperature- dependent field-effect characteristics

This paper experimentally investigates the subgap density of states (DOS) in p-type tin monoxide (SnO) thin-film transistors (TFTs) for the first time by using temperature-dependent field-effect measurements. As the temperature increases, the turn-on voltage moves in the positive direction, and the off-current and subthreshold slope continuously increase. We found that the conductivity of the SnO TFT obeys the Meyer–Neldel (MN) rule with a characteristic MN parameter of 28.6 eV−1 in the subthreshold region, from which we successfully extracted the subgap DOS by combing the field-effect method and the MN relation. The extracted subgap DOS from fabricated p-type SnO TFTs are exponentially distributed in energy, and exhibit around two orders of magnitude higher values compared to those of the n-type amorphous indium–gallium–zinc oxide TFTs.

Border trap characterization in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX gate dielectrics

We investigate the border traps in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX interfacial gate dielectrics. Border traps have been known as trapping centers of electronic carriers in field-effect transistors, and non-negligible hysteresis is observed in the bidirectional high-frequency capacitance-voltage curve with a slow ramp rate in both dielectric devices. From the gate voltage transient method and 1/f noise analysis, the spatially and energetically uniform trap distribution is obtained, and approximately four to five times higher border trap densities are extracted from SiNX dielectric devices than from the SiOX dielectric ones.

Low-Frequency Noise Properties in Double-Gate Amorphous InGaZnO Thin-Film Transistors Fabricated by Back-Channel-Etch Method

We investigated the low-frequency noise (LFN) properties of double-gate (DG) amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The LFN from all of the DG, top-gate (TG), and bottom-gate (BG) operation modes was well explained in the framework of the correlated carrier number-mobility fluctuation. However, the extracted noise parameters of the border trap density (N_T), Coulomb scattering coefficient (α_S), and apparent noise parameter (α_app) exhibited the highest values during the TG operation mode and the lowest values during the DG operation mode. The higher noise parameters (N_T, α_S, and α_app) from the TG operation mode compared with those from the BG operation mode were attributed to the poorer quality of the TG interface than the BG interface in the fabricated back-channel-etch-type DG a-IGZO TFTs. During the DG sweeping operation, the formation of the bulk accumulation channel was observed. The lowest noise parameters (N_T, α_S, and α_app) from the DG operation mode were considered to be a result of the current conduction through the bulk accumulation channel with a relatively low oxygen vacancy-related trap concentration.