Sang-Hun Song

Investigation of the charge transport mechanism and subgap density of states in p-type Cu2O thin-film transistors

We investigate the charge transport mechanism and subgap density of states (DOS) in p-type Cu2O thin-film transistors (TFTs) using the bias and temperature dependence of the drain currents. Among several charge transport mechanisms, the experimental data are well matched with a multiple trapping and release model, which suggests that the charge transport in the Cu2O TFT is mainly limited by trap states at grain boundaries or dielectric/semiconductor interface. The subgap DOS is extracted based on the Meyer-Neldel rule. Large density of subgap states is extracted, which is considered to be the reason of low mobility in fabricated Cu2O TFTs.

Effects of vacuum annealing on the optical and electrical properties of p-type copper-oxide thin-film transistors

We have investigated the effects of vacuum annealing on the optical and electrical properties of the p-type copper-oxide thin-film transistors (TFTs). The vacuum annealing of the copper-oxide thin-film was performed using the RF magnetron sputter at various temperatures. From the x-ray diffraction and UV-vis spectroscopy, it is demonstrated that the high-temperature vacuum annealing reduces the copper-oxide phase from CuO to Cu2O, and increases the optical transmittance in the visible part of the spectrum. The fabricated copper-oxide TFT does not exhibit the switching behavior under low-temperature vacuum annealing conditions. However, as the annealing temperature increases, the drain current begins to be modulated by a gate voltage, and the TFT exhibits a high current on?off ratio over 104?as the vacuum annealing temperature increases over 450??C. These results show that the vacuum annealing process can be an effective method of simultaneously improving the optical and electrical performances in p-type copper-oxide TFTs.

Effects of air-annealing on the electrical properties of p-type tin monoxide thin-film transistors

We have investigated the effects of air-annealing on the electrical performance of the p-type tin oxide thin-film transistors (TFTs). The air-annealing of the tin oxide thin-film was made using a mini furnace at various temperatures. From the x-ray photoelectron spectroscopy (XPS) and x-ray diffraction (XRD) data, it is demonstrated that the phase of tin oxide partially transforms from SnO to SnO2 with an air-annealing process, and it accelerates as the annealing temperature increases. The electrical performance of the p-type tin oxide TFT with a channel thickness of 25 nm exhibits much improved electrical performance when air-annealed at 230 °C for 1 h, but a decrease of the on-current is observed with an ambipolar operation in 260 and 290 °C air-annealed devices. Based on the XPS, XRD, and Hall measurement data, the reduced hole concentration inside the channel due to the recombination with electrons from SnO2 is believed to be the reason for the electrical performance improvement in 230 °C air-annealed p-type tin oxide TFTs, and a partial formation of n-type SnO2 channel is considered as the plausible reason for the ambipolar operation in tin oxide TFTs with high annealing temperatures. Our experimental results show that there is an optimum air-annealing temperature which can improve the electrical performance in p-type tin oxide TFTs.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Environment-Dependent Bias Stress Stability of P-Type SnO Thin-Film Transistors

We investigate the effects of environmental water and oxygen on the electrical stability of p-type tin monoxide (SnO) thin-film transistors (TFTs). Under negative gate bias stresses, there was a larger threshold voltage shift (ΔVth) in the devices that had been exposed to water than that for the devices that remained unexposed. However, under positive gate bias stresses, devices that had been exposed to water exhibited approximately the same ΔVth as what was observed in devices that had not been exposed. This phenomenon is attributed to the generation of residual-water-related hole traps near the valence band edge in SnO TFTs. In addition, we observed that the environmental oxygen partial pressure had very little effect on the electrical stability of p-type SnO TFTs under either negative or positive gate bias stresses. The weak chemisorption of oxygen molecules caused by high ionization energy can be a plausible mechanism for the oxygen insensitivity of negative gate bias-stress-induced instabilities, and the low electron concentration near the exposed back-channel of p-type SnO TFTs can possible explain the oxygen insensitivity of positive gate bias-stress-induced instabilities.

A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization

We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and drain bias stresses, and the damaged location is not limited to the drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and drain bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and drain bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and drain bias stresses in a-IGZO TFTs.

Active layer thickness effects on the structural and electrical properties of p-type Cu2O thin-film transistors

The authors investigated the effects of active layer thickness on the structual, optical, and electrical characteristics of p-type Cu2O thin-film transistors (TFTs). It was observed that as the channel thickness increases, the average grain size and root mean square roughness of the Cu2O thin films increase, but the optical transmittance notably decreases, especially in the short wavelength range below 500 nm. The p-type Cu2O TFT device exhibits the cleanest transfer function with only a small subthreshold slope when the channel thickness is 45 nm, whereas notable subthreshold slope humps are observed in the transfer curves for devices with thicker channels.

Fabrication of amorphous InGaZnO thin-film transistor-driven flexible thermal and pressure sensors

In this work, we present the results concerning the use of amorphous indium‐ gallium‐zinc‐oxide (a-IGZO) thin-film transistor (TFT) as a driving transistor of the flexible thermal and pressure sensors which are applicable to artificial skin systems. Although the a-IGZO TFT has been attracting much attention as a driving transistor of the next-generation flat panel displays, no study has been performed about the application of this new device to the driving transistor of the flexible sensors yet. The proposed thermal sensor pixel is composed of the series-connected a-IGZO TFT and ZnO-based thermistor fabricated on a polished metal foil, and the ZnO-based thermistor is replaced by the pressure sensitive rubber in the pressure sensor pixel. In both sensor pixels, the a-IGZO TFT acts as the driving transistor and the temperature/pressure-dependent resistance of the ZnO-based thermistor/pressure-sensitive rubber mainly determines the magnitude of the output currents. The fabricated a-IGZO TFT-driven flexible thermal sensor shows around a seven times increase in the output current as the temperature increases from 20 ◦ C to 100 ◦ C, and the a-IGZO TFT-driven flexible pressure sensors also exhibit high sensitivity under various pressure environments. (Some figures may appear in colour only in the online journal)

High Performance p-type SnO thin-film Transistor with SiO x Gate Insulator Deposited by Low-Temperature PECVD Method

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal SiO₂, a plasma-enhanced chemical vapor deposition (PECVD) SiNx, a 150 ℃-deposited PEVCD SiO x , and a 300 ℃-deposited PECVD SiO x . Among the devices, the one with the 150℃-deposited PEVCD SiO x exhibits the best electrical performance including a high field-effect mobility (=4.86 cm²/Vs), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localizedtrap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

Border trap characterization in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX gate dielectrics

We investigate the border traps in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX interfacial gate dielectrics. Border traps have been known as trapping centers of electronic carriers in field-effect transistors, and non-negligible hysteresis is observed in the bidirectional high-frequency capacitance-voltage curve with a slow ramp rate in both dielectric devices. From the gate voltage transient method and 1/f noise analysis, the spatially and energetically uniform trap distribution is obtained, and approximately four to five times higher border trap densities are extracted from SiNX dielectric devices than from the SiOX dielectric ones.