Chandan Bandyopadhyay

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic

This work addresses an ESOP-based reversible logic synthesis technique using paired cube approach. The input specification to this approach is a ‘.spec file’. In this work, initially, the first algorithm generates improved independent ESOP cubes. Next, the second algorithm performs the pairing of these improved ESOP cubes based on their structural similarity. It is observed that the proposed synthesis approach is very efficient mainly for those functions which do not have shared functionality between multiple outputs or have single output. Sharing of cubes between multiple outputs is not considered here. Experimental results show that the proposed approach has a significant impact on reduction of quantum costs of benchmark circuits. As we have mainly focused on the development of the synthesis technique for logic functions which do not have shared functionality between multiple outputs, we have compared our results with existing non shared-cube synthesis methods. Our approach is best fitted in that environment when function does not contain shared data between several outputs. The improved cube list generation algorithm is capable of generating reversible circuits for functions up to 16 input variables within reasonable time as we have taken ‘.spec file’ as input, whereas the cube pairing algorithm constructs reversible circuits for very large functions in negligible execution time.

A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit

This work proposes an ESOP-based technique for the synthesis of reversible circuit using a paired cube approach. In this method, initially we provide an ESOP as input and generate an optimized cube structure. Next, the pairing of ESOP cubes based on their structural similarity is performed to design improved reversible circuit using Toffoli gates. Experimental result shows that the paired cube synthesis approach is highly efficient primarily for the single output functions. Significant reduction of quantum cost is also achieved for those multi-output functions, which do not have shared functionality between multiple outputs. The proposed algorithm generates reversible circuits for large functions with reduced quantum cost in reasonable time.

All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit

In this work, we present all optical reversible implementation of Flip-Flops using semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. Improved design of MZI-based functionally reversible RS, D, JK, T and three different implementations of all optical functionally reversible MZI-based Master-Slave Flip-Flop using RS, D and JK Flip-Flop are presented. Detailed analysis and design complexities of all the functionally reversible optical Flip-Flops with improved optical costs have been reported.

ESOP-Based Synthesis of Reversible Circuit Using Improved Cube List

This work presents an ESOP-based synthesis technique for reversible logic circuit using improved cube list. Input specification for this method is a .spec file and it generates improved ESOP cubes which build the Toffoli network. The road map for generating this improved ESOP cubes is discussed in the paper. Each cube is independent in nature and can be shuffled according to needs. Sharing of cubes between multiple outputs has not been considered here. Our experiments demonstrate that the proposed approach is more effective than the previous on shared-cube synthesis methods. The algorithm is capable of generating reversible circuits for functions up to sixteen input variables within reasonable time.

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation

The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.

All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters

This work presents all optical reversible implementation of sequential counters using semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. All the designs are implemented using minimum number of MZI switches and garbage outputs. This design ensures improved optical costs in reversible realization of all the counter circuits. The theoretical model is simulated to verify the functionality of the circuits. Design complexity of all the proposed memory elements has been analyzed.

Diagnosis of SMGF in ESOP Based Reversible Logic Circuit

Testing of reversible circuit is an important issue to assure the quality and reliability of the reversible quantum circuit. Several fault models like Single Missing Gate Fault (SMGF), Partial Missing Gate Fault (PMGF), Multiple Missing Gate Fault (MMGF) and Repeated Gate Fault (RGF) have been predicated for better representation of faults in reversible quantum circuits. In this work, we develop an algorithm for diagnosis of Single Missing Gate Fault (SMGF) in exclusive-or sum of product (ESOP) based reversible circuit. Without using conventional testing technique where test vectors are generated to detect the fault, we present boolean expression based testing technique which produces the faulty gate details as a product term in boolean expression. The developed testing technique first detects the fault, then identifies the fault and finally corrects the erroneous part of the circuit to make it fault free.

Synthesis of ESOP-based reversible logic using negative polarity reed-muller form

The development of efficient techniques for reversible quantum circuit synthesis has received significant attention now-a-days due to recent emphasis on low power circuit design. This work presents two new deterministic methods, which evaluate the NPRM structure of logic functions. After extracting the structure, the synthesis of ESOP based reversible logic is performed using NPRM form. The first approach is based on transformation technique, whereas the second method is based on iterative reduction procedure. In both the approaches, we have derived the NPRM expression directly from an input truth table. Based on this expression, ESOP-based reversible circuit is synthesized.

Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams

Abstract The advancement of fabrication technology in VLSI (Very Large Scale Integration) and photonic industry has gained significant interest due to the feasibility of performing functional computations on-chip using ultra-high speed optical devices and low-power interconnects. Here, the necessity of optical circuits arises as they are inevitable components in developing optical Integrated Circuits (ICs). In this conjuncture, methodologies to design highly scalable optical circuits and their synthesis schemes have received interest. In recent years, several works and their findings have been reported in various research articles where researchers have mainly designed combinational and sequential memory elements using optical devices. The use of Binary Decision Diagrams (BDDs) to construct optical circuits has been reported recently. However, the costs of the resulting circuits are still rather high. Furthermore, they include a substantial amount of splitters, which is a significant drawback as they degrade the signal strength in the circuits. In this paper, we propose an improved design technique where we use BDDs to construct optical circuits. Rather than generating a single graph for multi-output functions, we consider individual graphs for each output separately which, afterwards are combined to realize the entire function. In our experiments, we find that this approach performs better in comparison to related techniques – a cost improvement of approx. 34% is observed on average. As these optical circuits are mainly designed with MZIs, beam combiners and beam splitters, the use of beam splitters in the circuit degrades the signal quality at the receiver end. To address this concern, in a second phase of our design, we make all the circuits free from splitters. Experimental results for both the design schemes are given and analyzed.

An Improved Circuit Synthesis Approach for ESOP-based Reversible Circuits

In this computing paradigms, the quantum computing has evolved as a promising platform for designing very fast computable circuits. In view of the improved design of such circuits, an efficient synthesis approach for circuits needs to be developed. As a direct synthesis of the quantum circuit is a bit complicated, the concept of reversible circuit appears which internally implements the quantum functionality, and to design better quantum circuit the corresponding reversible circuit have to be optimised. Considering this need, in this work, the authors develop an efficient reversible circuit synthesis scheme that constructs improved circuits by minimising the quantum cost. The entire work is completed in two phases. In the first phase, a circuit design scheme based on the best neighbour is implemented, where a function shares a portion of its own data with a chosen neighbour termed as the best neighbour and builds the shared structure. In the second phase, the designed circuit passes through an optimisation process which further reduces the cost metrics of the circuit. The experiment shows that the optimisation process substantially reduces the cost of the circuits to a great extent. At the end of the work, a comparative study with related works has also been presented.