Hafizur Rahaman

Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors

Dielectrically modulated tunnel FET (DMTFET)-based biosensors show higher sensitivity but lower subthreshold current compared with their dielectrically modulated FET counterpart. In this context, the effect of use of silicon-germanium (SiGe) source and n+-pocket-doped channel is investigated with the help of extensive device-level simulations. This paper explores the underlying physics of germanium composition variation in the source region, and doping concentration variation in n+-pocket region, from the perspective of biomolecule conjugation. The effects of source bandgap and tunneling length over the band-to-band tunneling component have been analyzed, and, subsequently, the sensing performance of DMTFETs has been estimated. The results show that SiGe-source DMTFET has significant superiority over n+-pocket DMTFET for attaining higher subthreshold current level while retaining acceptable sensitivity. Such sensitivity-current optimization has been studied for different gate and drain biases, and the suitable biasing range of operation has been indicated. In addition, the relative efficiency of SiGe source and n+-pocket-doped channel has been studied under different biomolecule sample specifications. Finally, the influence of trap-assisted tunneling on DMTFET sensing performance has been analyzed, and the comparative role of SiGe source and n+ pocket has also been indicated in this context.

Design of content addressable memory architecture using carbon nanotube field effect transistors

The work in this paper designs a 4-bit content addressable memory (CAM) architecture using carbon nanotube field effect transistors (CNTFETs). CAM is a special class of memory that is used to search a given data inside the memory. CAMs are used in high speed serach operations such as network routers. The proposed design is very efficient in terms speed and power as compared to its CMOS counterpart.

Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor

We investigate the effect of stacking order of bilayer black phosphorene on the device properties of p-MOSFET and n-MOSFET. Two layers of black phosphorus are stacked in three different orders and are used as channel material in both n-MOSFET and p-MOSFET devices. The effects of different stacking orders on electron and hole effective masses and output characteristics of MOSFETs, such as ON currents, ON/OFF ratio, and transconductance are analyzed. Our results show that about 1.37 times and 1.49 times increase in ON current is possible along armchair and zigzag directions, respectively, 55.11% variation in transconductance is possible along armchair direction, by changing stacking orders (AA, AB, and AC) and about 8 times increase in ON current is achievable by changing channel orientation (armchair or zigzag) in p-MOSFET. About 14.8u2009mV/V drain induced barrier lowering is observed for both p-MOSFET and n-MOSFET, which signifies good immunity to short channel effects.

A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simulation

In this paper, a novel device structure, operating on the principle of band-to-band tunneling, has been designed for near-infrared (1-1.5 μm) multispectral optical sensing applications. A drain current model based on line tunneling approach has been developed to illustrate the device operation. The results of the model are compared with the simulated data for devices with similar dimension and structure, indicating good accuracy of the developed model. Spectral response of the device is studied by estimating the relative values of its transfer-as well as output-characteristics, and also by measuring the variation of threshold voltage, V_T and ON-state current, I_ON. V_T and I_ON are found to be sensitive to wavelength variations at moderate gate doping levels. V_T is found to increase by ~40 mV and I_ON decreases by 35% for a change of illumination wavelength from 1 to 1.5 μm at a gate doping of 1 × 10¹⁸ cm^-3. Peak spectral sensitivity at an illumination intensity of 0.75 W/cm² is found to be 318.38, 2.02 × 10³, and 672.2 corresponding to the change in wavelength from (1-1.2 μm), (1.2-1.45 μm), and (1.45-1.5 μm), respectively.

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on Difference Expansion (DE) which is linear and whose running time is O (n). There are three different digital architectures proposed in this paper namely dataflow architecture, optimized dataflow architecture using pipelining and the modified architecture using pipelining. All the three design is implemented on Xilinx based FPGA. To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.

Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation

This work focuses on high performance voltage controlled current starved delay cell (CSDC) design. This delay cell will be used in Delay locked loop (DLL) based high precision Time-to-digital converter (TDC) implementation for Positron Emission Tomography (PET) application. DLL generates clocks of different phases. Sampling these clocks, sub-periodic time can be accurately measured as integer multiple of bin-size (unit delay difference between successive phases). Array of Delay locked loop (ADLL) can generate bin-size even below inverter delay for any technology node. With our delay cell, an ADLL can easily produce a bin size of 71.2ps using 100 MHz clock. Our delay cell consumes maximum static power of 267 uW with peak to peak delay mismatch of 2.86 ps and 0.684 ps rms delay mismatch. Unlike other delay cell, the transfer curve of our delay cell has lower slope and monotone decreasing function of control voltage below VTN. Dead-band in the transfer curve is inherently removed.

Analysis, modeling and optimization of transmission gate delay

Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic dependency on chain-length. This necessitates buffer insertion at depth 3 or 4 for chain of transmission gate in the current analysis methodology. In this paper, the dependency on two more factors such as fan-out and input-pattern are discussed. We show that the delay is dynamic and exponential depending on input-pattern and fan-out respectively. As a consequence, the insertion of buffer at proper depth is necessary for different fan-out configuration. A restoring mode transmission gate (RMTG) XOR gate is proposed which shows little dependency on fan-out and input patterns thereby eliminate the complexity of buffer insertion. The Spice simulation in 180nM UMC Technology shows that our proposed RMTG XOR is 13.21% and 31.34% faster, 51.63% and 1.72% power efficient compared to the conventional CMOS XOR and TG XOR respectively for a load capacitance of 10 fF. Our proposed model consumes less hardware compared to the conventional CMOS XOR.

A Device Simulation-Based Investigation on Dielectrically Modulated Fringing Field-Effect Transistor for Biosensing Applications

In this paper, a dielectrically modulated fringing field-effect-transistor (DMFFET) structure has been introduced as the transducer element for electrochemical biosensing applications, where the gate-induced fringing field has been exploited for transduction. This detection principle is different from that of the direct gate field modulation in conventional dielectrically modulated field-effect-transistor (DMFET)-based transducers. This paper explores the transduction mechanism from the electrostatics and carrier transport mechanism of DMFFET, in comparison with conventional double gated (DG) DMFET, based on extensive device-level simulation. The transducer response for the DMFFET/DG-DMFET structures has been estimated in terms of the drain current sensitivity, which is defined in the dB scale. In this paper, the effects of gate/drain biases have been investigated in details, and a strategy has been proposed for identifying suitable biasing ranges of operation based on half width at full maxima limit of sensitivity. The relative influences of electron trapping/de-trapping at the interfaces are also indicated on the transducer responses. Further, the role of different gate-related structural parameters of DMFFET has been considered for sensitivity-optimization. The comparative performance study with the reported DMFETs indicates the inherent superiority of DMFFET for transduction.

A Novel GNR Interconnect Model to Reduce Crosstalk Delay

In this research article, we have proposed a reduced thickness graphene nanoribbon (GNR) interconnect model to reduce crosstalk effects. The 10× higher current capability of GNR than copper (Cu) makes it an attractive choice to alleviate electro migration problem. The lower resistance of GNR is also an important factor to reduce interconnect delay. We have shown that the thickness of GNR interconnect can be reduced to reduce the crosstalk effects significantly without compromising the other benefits. Our analysis shows that the reduced thickness GNR interconnect can achieve ~2-3× reduction in crosstalk induced delay compared with Cu interconnects.

Effect of doping in p-GaN gate on DC performances of AlGaN/GaN normally-off scaled HFETs

This work presents the effect of p-type GaN gate doping concentration on the DC performances of 60nm gate length of AlGaN/GaN Normally-off HFET using 2D Atlas TCAD simulation. An extensive simulation is carried out for the proposed device to explore the parameters such as drain current, transconductance, energy band diagram and surface potential with respect to p-type GaN gate doping concentration (Pn). The concentration is varied from 5×1017 to 1×1019 and it is verified that with increase in Pn the drain current increases and transconductance decreases. An important conclusion has been figured out that when the Pn falls below 1×1018, the HFET device lost its normally-off mode which is not desirable for the high power switching application. Hence proper optimization of Pn is indispensable to preserve the normally-off mode operation and at the same time enhancing certain performance parameters.