Chando Park

Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond

This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.

Thermally Robust Perpendicular STT-MRAM Free Layer Films Through Capping Layer Engineering

In order to enable the spin-transfer torque (STT) magnetoresistive random access memory technologies, it is essential to control the thermal budget, perpendicular magnetic anisotropy, and magnetic damping parameter of perpendicular magnetic tunnel junction (pMTJ) thin films. This paper demonstrates the enhancement of pMTJ free layer (FL) properties through selective engineering of capping materials placed between a CoFeB FL and the top electrode. By introducing a capping layer of Mg or MgO, thermal budget and tunneling magnetoresistance (TMR) ratio are significantly improved over the conventional FL schemes due to reduced atomic intermixing at interfaces. In full-stack pMTJ films, thin Mg above the FL enables the TMR above 170% after 400 °C annealing. Capping via MgO increases the interface anisotropy, allowing for the use of thicker CoFeB FLs with magnetic damping constants as low as 0.003. We discuss the implications of these capping layer improvements and suggest that Mg and MgO show the potential for optimizing the FLs with high-thermal budget and good STT efficiency.

A Study on Practically Unlimited Endurance of STT-MRAM

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project

Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance

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Temperature Dependence of Critical Device Parameters in 1 Gbit Perpendicular Magnetic Tunnel Junction Arrays for STT-MRAM

write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs

We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.

HYBRID SYNTHETIC ANTIFERROMAGNETIC LAYER FOR PERPENDICULAR MAGNETIC TUNNEL JUNCTION (MTJ)

This paper investigates the temperature-dependent behaviors of critical device parameters in 1 Gb perpendicular magnetic tunnel junction (pMTJ) arrays from 25 °C to 125 °C. Despite the fact that pMTJ (45–50 nm in diameter) attributes are generally degraded at elevated temperatures, this paper suggests that an adequate combination of critical device parameters can be obtained through systematic materials and process engineering, including <inline-formula> <tex-math notation=LaTeX>

REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH

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Ultrathin perpendicular pinned layer structure for magnetic tunneling junction devices

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MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION

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