Jaesoo Ahn

Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond

This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.

A Study on Practically Unlimited Endurance of STT-MRAM

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project

Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance

> 10^{15}

A Self-Aligned Two-Step Reactive Ion Etching Process for Nanopatterning Magnetic Tunnel Junctions on 300 mm Wafers

write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

METHOD OF FORMING MAGNETIC TUNNELING JUNCTIONS

We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.

Temperature Dependence of Critical Device Parameters in 1 Gbit Perpendicular Magnetic Tunnel Junction Arrays for STT-MRAM

We demonstrated a self-aligned two-step reactive ion etching (RIE) process to pattern high density magnetic tunnel junction (MTJ) arrays. We did the RIE for the top electrode (TE) and stop in the middle of the tunnel barrier. A nitride conformal film was coated on the device pillars as a dielectric spacer. The conformal spacer protects the tunnel barrier from shorting by redeposition and provides a mask for the bottom electrode (BE) RIE. We used this process and completed perpendicular MTJ devices with our process flow. We tested the devices by measuring magnetic field switching and spin transfer torque switching. We get tunneling magnetoresistance (TMR) up to 100%, switching current as low as 60 μA at 100 ns, switching current density Jc0 as low as 2.5 × 106 A/cm2 and endurance above 109 for devices as small as 50 nm in diameter. The results are compared with devices from a TE RIE only process, and we find minimum damage was made by the BE RIE. We also discuss the size dependence of MTJ parameters such as TMR and free layer coercive field and offset field, which is very related to the RIE process.