Chandrasekhar Sarma

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Predicting substrate-induced focus error

The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.

Etch aware optical proximity correction: a first step toward integrated pattern engineering

We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch. As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC. Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer. We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC has been applied and compare these results with conventional resist based OPC schemes. Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored. We present a process optimization flow that incorporates model based retargeting into resolution enhancement technology selection, materials selection as well as lithographic and reactive ion etch process development.

Double exposure double etch for dense SRAM: a designer's dream

As SRAM arrays become lithographically more aggressive than random logic, they are more and more determining the lithography processes used. High yielding, low leakage, dense SRAM cells demand fairly aggressive lithographic process conditions. This leads to a borderline process window for logic devices. The tradeoff obtained between process window optimization for random logic gates and dense SRAM is not always straightforward, and sometimes necessitates design rule and layout modifications. By delinking patterning of the logic devices from SRAM, one can optimize the patterning processes for these devices independently. This can be achieved by a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper we show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 45nm node on fully integrated wafers, with more than adequate overlap of gate line-end onto active area. We have demonstrated that this process has adequate process window for sustainable manufacturing. For comparison purpose we also demonstrate a single exposure single etch solution to treat such dense SRAM cells. In 45nm node, the dense SRAM cell can also be printed with adequate tolerances and process window with single expose (SE) with optimized OPC. This is confirmed by electrical results on wafer. We conclude that DE2 offers an attractive alternative solution to pattern dense SRAM in 45nm and show such a scheme can be extended to 32nm and beyond. Employing DE2 lets designers migrate to very small tip-to-tip distance in SRAM. The selection of DE2 or SE depends on layout, device performance requirements, integration schemes and cost of ownership.

Three-dimensional physical photoresist model calibration and profile-based pattern verification

In this paper, we report large scale three-dimensional photoresist model calibration and validation results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although methods for calibrating physical photoresist models have been reported previously, we are unaware of any that leverage data sets typically used for building empirical mask shape correction models. . A method to calibrate and verify physical resist models that uses contour model calibration data sets in conjuction with scanning electron microscope profiles and atomic force microscope profiles is discussed. In addition, we explore ways in which three-dimensional physical resist models can be used to complement and extend pattern hot-spot detection in a mask shape validation flow.

Physical resist model calibration for implant level using laser-written photomasks

To reduce cost, implant levels usually use masks fabricated with older generation mask tools, such as laser writers, which are known to introduce significant mask errors. In fact, for the same implant photolithography process, Optical Proximity Correction (OPC) models have to be developed separately for the negative and positive mask tones to account for the resulting differences from the mask making process. However, in order to calibrate a physical resist model, it is ideal to use single resist model to predict the resist performance under the two mask polarities. In this study, we show our attempt to de-convolute mask error from the Correct Positive (CP) and Correct Negative (CN) tone CD data collected from bare Si wafer and derive a single resist model. Moreover, we also present the predictability of this resist model over a patterned substrate by comparing simulated CD/profiles against wafer data of various features.

Predicting and reducing substrate induced focus error

The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.

Single exposure is still alive: gate patterning at 45nm technology node

A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm technology node. They consist mainly of the introduction of a new software for optical proximity correction, the introduction of model based process window correction, the switch to model based etch proximity correction, and support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.