Derren Dunn

Dark Field Double Dipole Lithography (DDL) for back-end-of-line processes

The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25% smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Analysis of the three-dimensional ordering of epitaxial Ge quantum dots using focused ion beam tomography

Buried layers in quantum dot (QD) superlattices influence the position of QDs in the subsequently grown layers through strain field interactions. Since the strain interactions are complex, a three-dimensional reconstruction of the superlattice can enhance the fundamental understanding of self-organization mechanisms. We have studied the three-dimensional relationship of QDs using focused ion beam tomography. Analysis of the reconstruction is consistent with earlier models for self-organization. QDs on successive layers form above buried QDs. In certain cases, successive QDs in a column decrease in size, resulting in the elimination of the column while QDs in other columns grow in size.

Etch aware optical proximity correction: a first step toward integrated pattern engineering

We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch. As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC. Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer. We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC has been applied and compare these results with conventional resist based OPC schemes. Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored. We present a process optimization flow that incorporates model based retargeting into resolution enhancement technology selection, materials selection as well as lithographic and reactive ion etch process development.

3D physical modeling for patterning process development

In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective ground rules can be invaluable for early technology development. We will also demonstrate how the root cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Three-dimensional physical photoresist model calibration and profile-based pattern verification

In this paper, we report large scale three-dimensional photoresist model calibration and validation results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although methods for calibrating physical photoresist models have been reported previously, we are unaware of any that leverage data sets typically used for building empirical mask shape correction models. . A method to calibrate and verify physical resist models that uses contour model calibration data sets in conjuction with scanning electron microscope profiles and atomic force microscope profiles is discussed. In addition, we explore ways in which three-dimensional physical resist models can be used to complement and extend pattern hot-spot detection in a mask shape validation flow.

Nanoporous Materials Integration Into Advanced Microprocessors

Future microprocessor technologies will require interlayer dielectric (ILD) materials with a dielectric constant (κ-value) less than 2.5. Organosilicate glass (OSG) materials must be nanoporous to meet this demand. However, the introduction of nanopores creates many integration challenges. These challenges include 1) integrating nanoporous films with low mechanical strength into conventional process flows, 2) managing etch profiles, 3) processinduced damage to the nanoporous ILD, and 4) controlling the metal/nanoporous ILD interface. This paper reviews research to maximize mechanical strength by engineering optimal pore structures, controlling trench bottom roughness induced by etching and understanding its relationship to pore size, repairing plasma damage using silylation chemistry, and sealing a nanoporous surface for barrier metal (liner) deposition.

Analysis of the Three-Dimensional Nanoscale Relationship of Ge Quantum Dots in a Si Matrix Using Focused Ion Beam Tomography.

It is well documented that buried layers in quantum dot (QD) superlattices influence the position of quantum dots in the subsequently grown layers through strain field interactions (e.g. ). Using the Focused Ion Beam (FIB) tomographic technique we have reconstructed the 3D relationship of successive layers of coherent Ge QDs separated by epitaxial Si capping layers – a “QD superlattice”. Techniques such as Atomic Force Microscopy (AFM) and Scanning Tunneling Microscopy (STM) can only look at a single surface layer of QDs or, in the case of Transmission Electron Microscopy (TEM), look at a two-dimensional projection of a three-dimensional volume so that 3D relationships need to be inferred. Since the strain interactions are complex, an enhanced fundamental understanding of these self-organization mechanisms can more directly be obtained from full 3D reconstructions of these structures. By capping with Si at 300C we were able to grow QD superlattices with QDs tens of nanometers in height. This places them within the resolution of the FIB tomographic technique to reconstruct. Using the FIB we performed in-situ serial sectioning of the QD superlattice and then reconstructed the QD superlattice. The reconstruction was then analyzed to investigate the ordering of the QDs. Results from a reconstruction of a superlattice matrix will be presented with analysis of the self-ordering of the QDs. Observations of a novel self-limiting (in height) morphology, the quantum mesa, associated with the capping technique used will also be discussed.