Chang-Ho Shin

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAMs, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

A Study on the Site Plot Plan and Building Schematics of a Fusion DEMO Plant

Abstract To expedite realization of magnetic fusion energy with the tokamak concept, a parallel process of developing engineering technologies required to design, fabricate, construct, start up, and operate the fusion DEMO plant of Korea (K-DEMO Plant) at the same time with researching fusion science and technologies in KSTAR (Korean Superconductor Tokamak Advanced Research) and ITER (International Thermonuclear Experimental Reactor) was adopted in the fusion DEMO program of Korea (K-DEMO Program). As a part of these engineering studies, an exploratory study on the layout and building schematics of K-DEMO Plant have carried out in consideration of economic and safety aspects. The buildings of K-DEMO Plant are named and their volumes are estimated with an order of magnitude analysis based on the sizes of the buildings of ITER and nuclear power plants. This exploratory study on the layout and building schematics is also required to estimate the costs of K-DEMO Program and analyze its economic feasibility.

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty-cycle correction modes, CML-to-CMOS converters with wide range operation, active resonant loads at the end of WCK lane, and an on-chip de-emphasis circuit at a 4-to-1 multiplexer output as shown in Fig. 18.1.1. In addition, extra power pads improve the power distribution and release the frequency limitation at the memory core.

Re-Evaluation of the Neutronics Experiments for the ITER Shielding Blanket Using ENDF/B-VII, JEFF-3.1, and JENDL-3.3

Abstract MCNP calculations for a benchmark representative of the fusion blanket neutronics shielding in SINBAD (Shielding Integral Benchmark Archive Database) were performed by using the four nuclear data libraries, ENDF/B-VII, JEFF-3.1, JENDL-3.3, and FENDL-2.1. Neutron and gamma flux spectra were calculated at two positions in a mock-up of the ITER inboard shield system. The results were compared with each other and also compared with measured data from the neutronics experiments for the ITER shielding blanket. For neutron spectra calculations, it is noted that the MCNPX calculations using all libraries agree well with experiments at positions A and B. For gamma spectra calculations, an overall good agreement can be stated and the tendency of a slight underestimation with penetration depth is observed.