Seung-Jun Bae

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. Ronmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated Ronmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation

A CMOS LADFE (look-ahead decision feedback equalization) receiver with a pin-to-pin time skew compensation was proposed and implemented for high-speed chip-to-chip communication such as multi-drop DRAM interface. The look-ahead scheme in DFE input buffer increased the maximum data rate from 1.4 Gbps to 2.2 Gbps. Different sampling clock was synthesized for each pin by using an /spl times/2 over-sampling scheme. Active chip area per pin is 100 /spl mu/m/spl times/800 /spl mu/m with a 2.5 V, 0.25 /spl mu/m CMOS process.

Experimental and numerical research on condenser performance for R-22 and R-407C refrigerants

Abstract An experimental study of a fin and tube condenser was performed using two different configurations of condenser paths (U and Z type) and two kinds of refrigerants (R-22 and R-407C) as working fluids. An integral test facility was constructed to evaluate the heat transfer capacity of the air and refrigerant sides of the condenser. An uncertainty study was also performed. A numerical code was developed, using a section-by-section analysis scheme in which mal-distribution on the air side and temperature gliding on the refrigerant side could be considered along the tube-length direction. Different condenser capacities were obtained from both the experimental and numerical results, depending on the paths and refrigerants used. R-22 performed better than R-407C for the Z-type path configuration, but no significant difference was found between results using either refrigerant in the U-type path configuration. On average, the numerical results obtained with R-22 were 10.1% greater than experiment data; using R-407C, results were 10.7% less than experiment data. The numerical code can be used as a design tool to develop better condenser paths.

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

A 3Gbit/s/pin 8b parallel 4-drop single-ended DRAM transceiver is implemented in a 0.25 /spl mu/m CMOS process. Digital calibrations are performed for equalization and compensation of data skew and offset voltage. A continuously active on-die termination is used to reduce reflections. A phase detector is proposed for the digital DLL to achieve the S/H time of 10ps.

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply.

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-/spl mu/m CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370/spl times/510 /spl mu/m/sup 2/, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively.

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity.

A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

A 2Gb/s integrating 2-tap decision feedback equalizer receiver is implemented in a 0.25/spl mu/m CMOS process to reduce high- and low-frequency noise for multi-drop single-ended signaling system. Voltage margin is enhanced by 110%(90%) for a stubless channel at 2Gb/s (an SSTL channel at 1.2Gb/s).

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.