Chang-Oh Jeong

42.2: World's Largest (15-inch) XGA AMLCD Panel Using IGZO Oxide TFT

The worlds largest (15-inch) XGA active matrix liquid crystal display (AMLCD) panel made with IGZO TFTs (W/L=29.5/4 μm) was fabricated and evaluated with the field effective mobility of 4.2±0.4 cm2/V-s, Vth of −1.3±1.4V and sub-threshold swing (SS) of 0.96±0.10 V/dec. for a manufacturing-oriented process, the main factors affecting threshold voltage (Vth) of the IGZO thin film transistors (TFT) are investigated. On the glass surface, thicker regions of IGZO film have a negative threshold voltage shift. A dry etching process of molybdenum source and drain (S/D) causes negative shift of the average threshold voltage compared to wet etching in the bottom gate back channel etched TFTs. However, optimization of SiOx passivation and subsequent annealing shift average Vth positively and reduce Vth variation.

Improvement in the bias stability of amorphous indium gallium zinc oxide thin-film transistors using an O2 plasma-treated insulator

The effects of an O2 plasma-treated SiNX-based insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) were investigated. We tried to improve the interfacial characteristics by reducing the trap density between the SiNX gate insulator and a-IGZO channel by the O2 plasma treatment. The plasma treated-device performances were remarkably improved. The drastic improvements obtained for the O2 plasma-treated a-IGZO TFTs included excellent bias stability as well as a high field effect mobility (μFE) of 19.4 cm2/V s, an on/off current (ION/IOFF) of 108, and a subthreshold value (S) of 0.5 V/decade.

Application of DC Magnetron Sputtering to Deposition of InGaZnO Films for Thin Film Transistor Devices

This is the first report demonstrating that InGaZnO (IGZO) thin films deposited using DC magnetron sputtering can be used for the active channel layer of a thin film transistor (TFT) device. We have determined the process conditions at which dc magnetron sputtering provides a high growth rate and smooth surface for IGZO thin films using an InGaZnO4 ceramic target. The effect of the oxygen content on the electrical properties of the IGZO thin films was examined. The field effect mobility of the TFT device fabricated with the IGZO thin film deposited at an optimum oxygen partial pressure of 6% was 9.2 cm2 V-1 s-1. The operation mechanism of IGZO-TFT was explained on the basis of the band diagram with flat band voltage. Moreover, we evaluated the effects of bias stress on transistor performance and showed that device instability appears to be a result of the carrier trapping and releasing in the gate insulator layer under high gate voltage stress.

Effects of oxygen contents in the active channel layer on electrical characteristics of ZnO-based thin film transistors

The authors report the fabrication and characteristics of thin film transistors with ZnO channel layers (ZnO TFTs) having different oxygen contents. Also, the authors define the operation mechanism of ZnO TFTs as the variation of oxygen contents in the ZnO channel layer. The ZnO thin films were deposited on SiO2∕n-Si substrate by dc magnetron sputtering at various oxygen partial pressures. Effects of oxygen contents in ZnO thin films on the electrical performance of ZnO TFTs with bottom gate structure were investigated. The ZnO thin films deposited at oxygen partial pressures of 40% exhibit a nonstoichiometric system in an oxygen rich state, resulting in resistivity as high as 105Ωcm. ZnO TFTs with this channel layer exhibited depletion mode, turn on voltage of −15V, on-off current ratio of ∼106, and field effect mobility of 0.88cm2∕Vs. This research implied that an attractive application for TFTs involves their use as select transistors in individual pixels of an active-matrix liquid-crystal display.

Advanced four‐mask a‐Si TFT array fabrication process using improved materials

In order to achieve higher-performance and lower-cost a-Si TFT array manufacturing, an advanced four-mask fabrication process using low-resistant metals, a new pixel electrode material, and improved unit processes was developed. Slit (or gray-tone) photolithography, in combination with a continuous all-in-one dry-etching process, solved the chronic problems of the current four-mask process. Additionally, a new combination of materials and a new wet etchant for the gate-line patterning made it possible to achieve stabilized wet-etching results and reduced the number of process steps. Our advanced a-Si TFT-array fabrication process is applicable to both notebook and monitor displays, and will further improve the market position of TFT-LCDs by improved performance and manufacturing process simplification.

Adhesion, passivation, and resistivity of a Ag(Mg) gate electrode for an amorphous silicon thin-film transistor

The effect of Mg in Ag(Mg)/SiO 2 /Si multilayers on the adhesion, passivation, and resistivity following vacuum annealing at 200-500 °C has been investigated. The annealing of Ag(Mg)/SiO 2 /Si multilayers produced surface and interfacial MgO layers, resulting in a MgO/Ag/MgO/SiO 2 /Si structure. The formation of a surface MgO/Ag bilayer structure provided excellent passivation against air and CF 4 plasma chemistry. In addition, the adhesion of Ag to SiO 2 was improved due to the formation of an interfacial MgO layer resulting from the reaction of segregated Mg with SiO 2 . However, the negligible solubility of Si in Ag prevented the dissolution of free silicon into the Ag(Mg) film produced from the reaction Mg + SiO 2 = MgO + free Si, which in turn limited the reaction between Mg and SiO 2 , which led to a decrease in the adhesion of Ag to SiO 2 at the higher temperature. The use of an O 2 plasma prior to Ag(Mg) alloy deposition on SiO 2 produced an oxygen-rich surface on the SiO 2 which allowed for the enhanced reaction of the segregated Mg and SiO 2 at the surface, thus resulting in markedly increased adhesion properties.

High-mobility material research for thin-film transistor with amorphous thallium–zinc–tin oxide semiconductor

The applicability of thallium–zinc–tin oxide (TlZnSnO) as a channel material for a thin-film transistor (TFT) was investigated by first-principles simulation and cosputtering experiment with XZnSnO (X = Al, Ga or In). The electron effective mass (m*) of Tl0.4ZnSnO was simulated to be ~0.153, which is much smaller than that of In0.4ZnSnO (0.246). An In0.4ZnSnO TFT exhibited a mobility (μ) of 32.0 cm2 V−1 s−1 in the experiment; therefore, the Tl0.4ZnSnO TFT was expected to have a higher mobility of approximately 50 cm2 V−1 s−1 following the relation (μ ∝ 1/m*). Moreover, the Tl-related oxide semiconductor would provide better TFT stability because its oxide vacancy is more stable than that of an In-related oxide semiconductor.

Effects of a Ni alloying element on Al?Ni metallization

The effect of the Ni content (2?18 at.% Ni) in Al thin films on their resistivity, hillock formation and Al3Ni compound formation was investigated. The as-deposited Al?Ni-alloy films showed high elastic strains which increased with increasing Ni content. In addition, the annealing of the supersaturated Al?Ni-alloy thin films yielded two phases: Al3Ni and Al with strong (2?2?0) and (1?1?1) textures, respectively, suggesting that the nucleation of (2?2?0) Al3Ni is closely associated with (1?1?1) Al. The resistivity of the as-annealed Al?Ni-alloy films varied as functions of the volume fraction and grain size of the two phases, which were determined by the Ni content and annealing temperature, respectively. The hillock formation was effectively suppressed when a small amount of Ni was added to the Al alloy. The results showed that a Ni content of less than approximately 4.5 at.% produced hillock-free Al-alloy thin films with a low resistivity of less than 6.0 ?? cm upon annealing at 350 ?C.

33.3: A 14.1‐Inch WXGA+ LCD Panel Using Hybrid Silicon Thin Film Transistors

A hybrid silicon technology (HyST) thin film transistor (TFT) process using a diode-pumped solid state (DPSS) laser has been developed by implementing low-temperature poly-Si (LTPS) TFTs with a-Si:H TFTs on the same substrate. HyST TFTs are deployed on the peripheral area of a panel for integrated gate driver circuits and a-Si:H TFTs are used as switching devices for pixels in the active display area. This technology is based on the current a-Si:H TFT fabrication processes without additional ion-doping and activation processes. Field effect mobilities of 4 ∼ 5 cm2/V⋅s and 0.5 cm2/V⋅s for HyST and a-Si:H TFTs, respectively, are obtained. Low power consumption, high speed, small integration area, high reliability, and low photosensitivity are achieved by means of HyST TFTs, compared to gate driving circuits integrated with a-Si:H TFTs. A 14.1-inch WXGA+ (1440×900) LCD panel has been demonstrated using the new HyST TFT process.

Development of a new hybrid silicon thin‐film transistor fabrication process

Abstract A new hybrid silicon thin‐film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low‐temperature poly‐Si (LTPS) and a‐Si:H TFTs on the same substrate as a backplane of the active‐matrix liquid crystal flat‐panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the active‐matrix LCD panel for the gate driver circuit, and a‐Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a‐Si:H TFT fabrication process in the bottom‐gate, back‐channel etch‐type configuration. The ion‐doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of 4∼5 cm2/V·s and 0.5 cm2/V·s for the LTPS and a‐Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1” WXGA+(1440 × 900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a‐Si:H TFT gate driver integration circuit