Chang-Seok Choi

Two-parallel Reed-Solomon based FEC architecture for optical communications

This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A high-speed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160MHz and has a throughput of 41Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400MHz and has a throughput of 102Gb/s for 0.18-µm CMOS technology.

An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform

This paper presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement an autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This reconfigurable FIR filter design method using Xilinx Virtex-4 FPGA shows the configuration time improvement, and flexibility by using the dynamic partial reconfiguration method.

High-speed low-complexity Reed-Solomon decoder using pipelined Berlekamp-Massey algorithm

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm. Also, this paper offers technique which is about efficient method of pipelining at the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in Syndrome computation block, key equation solver (KES) block, Forney and Chien search blocks so as to enhance clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm has been designed and implemented with IBM 90-nm CMOS standard cell technology in a supply voltage of 1.2 V. The proposed RS decoder operates at a clock frequency of 690 MHz and has a throughput of 5.52 Gb/s. The proposed architecture requires approximately 18% fewer gate counts than architecture based on the pipelined degree-computationless modified Euclidean (pDCME) algorithm [5].

A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform

This paper presents a self-reconfigurable adaptive FIR filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, advantages of configuration time allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for realization and autonomous adaptation of FIR filters, and processes the optimal digital signal processing algorithms, which are the low-pass, band-pass and high-pass filter algorithms with various frequencies, for noise removal operations. The proposed stand-alone self-reconfigurable system using Xilinx Virtex4 FPGA and Compact-Flash memory shows the improvement of configuration time and flexibility by using the dynamic partial reconfiguration techniques.

High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture

This paper presents a high-speed low- complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90- nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

Low-complexity folded FIR filter architecture for ATSC DTV tuner

This paper presents an efficient folded finite-impulse response (FIR) filters for digital TV tuner. DTV receivers are widely used in many electronic systems such as HD-TV, set-top box, PDA and cell phones. The DTV tuner that is a major power expender and costly device in the receiver selects the desired signals from many signals available and down-converts them. To reduce hardware complexity, the folded architectures are proposed and Common Subexpression Elimination (CSE) methods based on binary representation of coefficients for the high order FIR filters are used in this paper. The implementation result show that proposed folded FIR filter operates at a clock frequency of 200MHz and has 60% less hardware complexity than unfolded structure for 90-nm CMOS technology. Also, the proposed folded architecture has 12% less complexity than the other folded architecture.

40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications

This paper presents a high-speed forward error correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 40-Gb/s optical communication systems. A high-speed two-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 40-Gb/s RS FEC architecture. The proposed 40-Gb/s RS FEC has been implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V and Xilinx Virtex4 FPGA. The implementation results show that 16-Ch. RS-based FEC architecture can operate at a clock frequency of 160 MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also RS-based FEC operates at a clock frequency of 400 MHz and has a throughput of 102-Gb/s for 0.18-mum CMOS technology.

A Partial Self-Reconfigurable Adaptive FIR Filter System

This paper presents a self-reconfigurable adaptive FIR Filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, configuration time advantage allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for realization and autonomous adaptation of FIR filters, and processes the optimal digital signal processing algorithms, which are the low-pass, band-pass and high-pass filter algorithms with various frequencies, for noise removal operations. The proposed stand-alone self-reconfigurable system using Xilinx Virtex4 FPGA and Compact-Flash memory shows the improvement of configuration time and flexibility by using the dynamic partial reconfiguration techniques.

Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems

In this paper, we propose a soft-decision-based FEC scheme which is the concatenation of a non-binary LDPC (NB-LDPC) code and hard-decision FEC code having a compatibility with existing OTU-4 frame structure. The proposed concatenated NB-LDPC + RS frame structure is also provided and the entire frame size is 18,368 bytes. The proposed NB-LDPC(2304,2048) code over GF(24) provides a superior performance at the higher BER region and can be concatenated with HD-FEC code. The simulation result shows that the proposed concatenated NB-LDPC(2304,2048) and RS(255,239) FEC can provide a superior NCG performance over 10.3 dB at a post-FEC BER 10−15 and over 10.8 dB with enhanced HD-FEC in the outer code. As a result, the proposed NB-LDPC codes are expected to be strong FEC candidates of soft-decision FEC for 100Gb/s optical transmission system.

Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications

This paper presents a high-speed Forward Error Correction (FEC) architecture based on the concatenated BCH code for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98dB net coding gain at 10−12 corrected bit error rate without additive overhead as compared with the Reed-Solomon(255, 239) standardized in ITU-T G.975 and G.709. This architecture has been implemented with 90-nm CMOS standard cell technology in a supply voltage of 1.1V. The implementation results show that the concatenated BCH Super-FEC architecture can operates at a clock frequency of 400MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.