Jong-Yoon Shin

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders

This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.

40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications

This paper presents a high-speed forward error correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 40-Gb/s optical communication systems. A high-speed two-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 40-Gb/s RS FEC architecture. The proposed 40-Gb/s RS FEC has been implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V and Xilinx Virtex4 FPGA. The implementation results show that 16-Ch. RS-based FEC architecture can operate at a clock frequency of 160 MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also RS-based FEC operates at a clock frequency of 400 MHz and has a throughput of 102-Gb/s for 0.18-mum CMOS technology.

Field Trial of 112 Gb/s Dual-Carrier DQPSK Channel Upgrade in Installed 516 km of Fiber Link and ROADM

A field trial of 100GE signal transmission using dual-carrier differential quadrature phase shift keying (DC-DQPSK) based optical transceiver is demonstrated for 100 Gb/s metro area network. Neither high-end ADC/DSP nor fast optical polarization tracking is required in the DC-DQPSK based optical transceiver, which results in low electrical power consumption of ~ 35 W. The measured OSNR sensitivity of DC-DQPSK optical transceiver at the BER of 10- 3 is 18.3 dB. After the transmission through 516 km of installed fiber and ROADM, an error-free transmission of 100GE signal over 106 hours with OTU4 framer and forward error correction (FEC) decoding proves feasibility of DC-DQPSK optical transceiver for 100G metro network applications.

Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications

This paper presents a high-speed Forward Error Correction (FEC) architecture based on the concatenated BCH code for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98dB net coding gain at 10−12 corrected bit error rate without additive overhead as compared with the Reed-Solomon(255, 239) standardized in ITU-T G.975 and G.709. This architecture has been implemented with 90-nm CMOS standard cell technology in a supply voltage of 1.1V. The implementation results show that the concatenated BCH Super-FEC architecture can operates at a clock frequency of 400MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.

Optical supervisory channel subsystem for 1.6T WDM transmission system

The optical supervisory channel (OSC) in WDM (Wavelength Division Multiplexing) transmission systems is used for OAM (Operations, Administrations and Management) function like overhead information in SOH (Synchronous Digital Hierarchy). We present supervisory information contents and alarm propagation procedure in our 1.6T WDM transmission system. Also, this paper describes the OSC frame structure and the OSC subsystem configuration that can provide reliable and effective operation and maintenance capability.

100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300 MHz and has a throughput of 115-Gb/s for 0.13-mum CMOS technology.

A Design and Implementation of OTU4 Framer for l00G Ethernet

This paper discusses standardization activities, requirements and enabling technologies for 100G Ethernet and 100G OTN. The need of 100Gbps transport capacity has been gaining greater interest from service providers and carrier vendors. Moreover, optical transport networks based on OTN/DWDM are changing their properties to apply Ethernet traffic which is dramatically increasing. We realize and experimentally demonstrate OTU4 framer with commercial FPGA. The key features of the realized OTU4 framer are parallel signal processing function, multi-lane distribution function, GMP function and FEC function. The realized OTU4 framer has the large signal processing capacity of 120Gbps, which allows to transport about 120Gbps client signals such as Ethernet and Ethernet. The realized OTU4 framer has the advantages to quickly adjust to changing markets and new technologies by using commercial FPGA instead of ASIC.

High speed optical transmission R&D in ETRI

In this paper, after a brief introduction of related Korean industrial situation, 40G/100G optical transmission R&D efforts in ETRI are described.