Chang Woo Byun

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of −9 V, and a subthreshold swing (S) of 1.4 V/dec.

High performance low temperature polycrystalline Si thin-film transistors fabricated by silicide seed-induced lateral crystallization

A novel and simple crystallization method for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using Ni silicide seed-induced lateral crystallization (SILC) was proposed in this study, and it includes no additional deposition and/or etching processes that are not found in the fabrication of conventional metal-induced lateral crystallization (MILC) TFTs. The poly-Si thin films crystallized by SILC were characterized by x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and Micro-Raman spectroscopy. The electrical properties were obtained from ID-VG transfer curves and the interface trap density was determined by Levinson plot analysis. The results show that SILC poly-Si films have lower Ni contamination, better crystallinity, and higher crystalline fraction than MILC poly-Si films. The p-channel SILC poly-Si TFTs exhibited a mobility of 66 cm2/V·s, a minimum leakage current of 3.4 × 10−11 A at VD = −5 V, a subthreshold slope of 0.85 V/dec, and a maximum on/off ratio of 5.0 × 106, all of which resulted in a high-performance device which surpassed conventional MILC poly-Si TFTs.

Effect of Ni silicide density on electrical performance of silicide-induced crystallized polycrystalline silicon thin-film transistors

The electrical performance of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) fabricated by silicide-induced crystallization (SIC) is greatly affected by metal contamination such as Ni silicide. In this paper, the effect of Ni silicide density on the SIC poly-Si TFTs is investigated by in-situ Ni silicidation at room temperature, 100°C, 200°C, and 300°C, respectively. It was observed that grain size of fully crystallized polycrystalline silicon (poly-Si) decreased with the increase of in-situ silicidation temperature. This is due to an increase in the density of nucleation sites for crystallization. As a result, grain boundaries and interface trap-state densities were significantly increased and electrical properties such as subthreshold slope, on-state current and field effect mobility were drastically degraded.

Gettering of Ni silicide to minimize the leakage current in metal-induced crystallized polycrystalline silicon thin-film transistors

AbstactMetal-induced lateral crystallization (MILC) technology has been regarded as the only alternative for low temperature polycrystalline silicon (poly-Si) since it became apparent that laser technology still had intrinsic problems for industrial use. The only problem with MILC poly-Si thin-film transistors (TFTs) is a relatively large leakage current, which has been reported to be due to Ni silicides trapped at the grain boundaries of the poly-Si thin film on the way to lateral crystallization. In this work, the trapped Ni silicides have been removed by catalytic phase transformation. This process has ameliorated not only the problem of leakage current but it has also improved other electrical properties, such as field effect mobility and subthreshold slope by gettering of the Ni silicide.

Preparation and characterization of Nickel Oxide thin films by direct current reactive magnetron sputtering at different substrate temperatures

The influence of substrate temperature on the properties NiO films, prepared by dc reactive magnetron sputtering technique, is studied by various characterization methods. X-ray diffraction studies revealed that the crystal structure is highly influenced by the substrate temperature. The optical results indicated that the optical transmittance and band gap of the films increased with the increase of substrate temperature up to 523 K. The optical band gap of NiO films decreases from 3.82 to 3.70 eV with the increase of substrate temperature from 523 to 723 K. The electrical resistivity decreased with the increase of substrate temperature from 303 to 723 K, whereas carrier concentration and Hall mobility increased with increasing the substrate temperature.

Integration of large single-grain Pb(Zr,Ti)O3 into low-temperature polycrystalline silicon thin-film transistors for system-on-glass display

A large single-grain Pb(Zr,Ti)O3 (PZT) film was integrated into low-temperature polycrystalline silicon (poly-Si) thin-film transistors fabricated on a glass substrate. The poly-Si was crystallized by NiSi2 seed-induced lateral crystallization (SILC). The SILC poly-Si had a superior electrical performance to other crystallization methods as a result of its high crystalline volume fraction (91.2%). PZT with a perovskite phase is generally obtained at 800 °C, which is not suitable for glass substrates. Therefore we developed a low-temperature perovskite PZT using an artificially controlled seeding process. An artificially controlled nucleation seed was first formed by rapid thermal annealing at 650 °C in 1 s pulses and a single seed was then grown in a tube furnace at 550 °C for 2 h. The resulting device had a large memory window (3.5 V) and a highly reliable memory operation. This approach could potentially be applied to the next generation of non-volatile memory devices as well as in integrated system-on-glass displays.

A hybrid ferroelectric-flash memory cells

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V−1 s−1 of field-effect mobility, 190 mV dec−1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to −5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion ...

Large-grained Pb(Zr,Ti)O3 integrated into polycrystalline-silicon thin-film transistor for system-on-glass applications

In this work, the authors fabricated 1-transistor ferroelectric random access memory based on polycrystalline-silicon (poly-Si) on a glass substrate. A novel technique was used to form a large single-grained Pb(Zr,Ti)O3 (PZT) layer as the gate insulator. Generally, the crystallization temperature of PZT is 800 °C, which is beyond the limits for a glass substrate; however, here the authors developed a selectively nucleated lateral crystallization technique to minimize the crystallization temperature and grow 40 μm grains of PZT. Pt layer using rapid thermal annealing at 650 °C for a short time, and grew a single seed by tube-furnace at 550 °C for 2 h. Our device demonstrated excellent electrical properties with long retention time, which only decreased by 9% after 104 s, and good fatigue characteristics, which only decreased by 4% after 104 cycles.

Reduced Trap-State Density of Ni-Silicide Seed-Induced Crystallized Poly-Si TFTs by Gettering

Polycrystalline silicon thin-film transistors (TFTs) fabricated by seed-induced crystallization (SIC) have large leakage currents due to defects that consist of Ni impurities. Here, we describe a novel method of gettering to remove Ni impurities using a Si gettering layer that is separated from the active layer by a chemical SiO2 etch stop interlayer formed by dipping into H2SO4. The leakage current, the on/off ratio, and a channel breakdown voltage were greatly improved. These results were explained by lowered trap-state density in the channel.

Effect of Dopant Concentration in Lightly Doped Drain Region on the Electrical Properties of N-Type Metal Induced Lateral Crystallization Polycrystalline Silicon Thin Film Transistors

In this study, the effect of dopant concentration in lightly doped drain (LDD) region on the electrical properties of N-type gate insulator doping mask (GIDM) LDD metal-induced lateral crystallization (MILC) polycrystalline silicon thin film transistors (TFTs) was investigated. In order to find the optimum value for the dopant concentration in LDD region, we analyzed the electrical properties of LDD MILC TFTs with different dopant concentration in LDD region. The dopant concentrations in LDD regions of the TFTs were measured using secondary ion mass spectroscopy (SIMS). From the electrical properties and the SIMS data of the TFTs, it has been found that for the N-type GIDM LDD MILC TFTs with the LDD length of about 1.5 µm, the dopant concentration in LDD region should be in the range between 1019 and 3×1020/cm3 to ensure the suppression of off-state leakage current without device performance degradation.