Hyung Yoon Kim

Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystalline-Silicon Thin-Film Transistors Fabricated via Metal-Induced Lateral Crystallization

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT.

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

High-Performance Poly-Si Thin-Film Transistor With High-

High-performance poly-Si thin-film transistors (poly-Si TFTs) with metal-induced laterally crystallized (MILC) poly-Si channel and high-k ZrTiO4 (ZTO) gate dielectric are shown for the first time. The MILC poly-Si and ZTO dielectric showed smooth interface (~1.8 nm) with a low interfacial layer and 4.1 nm of effective-oxide thickness. The electrical performance of MILC poly-Si TFT with ZTO exhibited low threshold voltage of -0.5 V, steep subthreshold slope of 0.25 V/decade, high ION/IOFF of 1.8 × 107, and high field-effect mobility of 250 cm2/Vs. These characteristics correspond to the best performance of the poly-Si TFTs with high-k gate dielectric reported so far. Moreover, the driving current and field-effect mobility of poly-Si TFT with ZTO gate dielectric were ten times higher than that of poly-Si TFT with deposited-SiO2 gate dielectric.

k

Being able to control grain boundaries during the phase transformation when processing a ferroelectric thin-film is crucial for the successful development of practical multibit ferroelectric memory. A novel development of ferroelectric thin-film crystallization processing for realizing epitaxial-like single crystals via artificial nucleation by Pt-seeding is reported here. Dividing the nucleation and growth mechanism by Pt-seeding, it is possible to obtain large and uniform rectangular-shaped ferroelectric grains, large enough to fabricate a field-effect transistor (FET) in the inside of the crystal grain. The fabricated ferroelectric FET, Pt/Pb(Zr,Ti)O3/ZrTiO4/Si, showed a large memory window (∼2.2 V), a low operation voltage (∼6 V), and an ultra-fast program/erase speed (∼10−6 s). Moreover, there was no degradation after 1015 cycles of bipolar fatigue testing and the sample even showed a long retention time after 1 yr. All of these characteristics correspond to the best performance among all types of fe...

ZrTiO 4 Gate Dielectric

In order to improve the kinetic performance of LiFePO4-based Li-ion batteries, three dimensional metal foams were used as positive current collector. In the case of conventional Ni foam, the organic electrolyte of the cell was decomposed with the ionization of Ni during charge and discharge. The low tolerance of Ni was solved by using NiCrAl foam which was manufactured by alloying NiCrAl powder with Ni foam. From the electrochemical analysis, it shows that the kinetic performance of the cell by using a three dimensional NiCrAl foam was much superior to that in the case of conventional foil type.

Multibit ferroelectric field-effect transistor with epitaxial-like Pb(Zr,Ti)O3

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Metal Foam as Positive Electrode Current Collector for LiFePO4-Based Li-Ion Battery

Controlling the grain-boundary of ferroelectric thin-film is significantly important for realizing ultimate multibit-FeRAM, when a ferroelectric thin-film deposited by radio-frequency reactive magnetron sputtering is integrated into silicon-based devices. A novel crystal-growth process of a ferroelectric thin-film using platinum (Pt)-seed matrix is developed for dividing the nucleation and growth of PbZr0.52Ti0.48O3 (PZT), which cannot be observed in the classical nucleation and growth of PZT. Locating artificial nucleation seeds using Pt-seeds in a desirable position enables one to obtain a large single-grain PZT (~40 μm) that is large enough to fabricate a field-effect transistor (FET)-type FeRAM. The fabricated FeRAM with a Pt/PZT/ZrTiO4(ZTO)/p-Si structure showed a wide memory window (~1.8 V), low operation voltage (~6 V), ultra-fast Program/Erase (P/E) switching speed (~10–7 s), and a stable multibit operation controlled by local polarization. In addition, the FeRAM showed no degradation even after cycling the P/E more than 1011 times in all multibit states, and the retention time was expected to have a wide memory window even after 10 years in all multibit states. These characteristics show great potential for the multi-bit FeRAM, which is difficult to expect a reliable operation with large grain-boundaries.

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor.

We developed a novel technique to reduce the gate-induced drain leakage (GIDL) current by a simple method using the 350-nm ultraviolet (UV) irradiation at 300 W. The pinning GIDL current was reduced from 94% without any pinning, and the threshold voltage was shifted from -6 to -2 V after 1000 s. The mechanism of the GIDL current reduction is deeply investigated and confirmed by the density of states, drain activation energy (Ea), and extraction of grain-boundary traps (Nt). The density of acceptor-like states increases with the increase in UV exposure. The shift in Fermi level away from the valence band to the conduction band under the UV irradiation is the main proposed mechanism for the GIDL current reduction.

Ultimate multibit 1T-FeRAM with selectively nucleated grown single-grain PbZr0.52Ti0.48O3 for very-large-scale-integrated memory

A large single-grain Pb(Zr,Ti)O3 (PZT) film was integrated into low-temperature polycrystalline silicon (poly-Si) thin-film transistors fabricated on a glass substrate. The poly-Si was crystallized by NiSi2 seed-induced lateral crystallization (SILC). The SILC poly-Si had a superior electrical performance to other crystallization methods as a result of its high crystalline volume fraction (91.2%). PZT with a perovskite phase is generally obtained at 800 °C, which is not suitable for glass substrates. Therefore we developed a low-temperature perovskite PZT using an artificially controlled seeding process. An artificially controlled nucleation seed was first formed by rapid thermal annealing at 650 °C in 1 s pulses and a single seed was then grown in a tube furnace at 550 °C for 2 h. The resulting device had a large memory window (3.5 V) and a highly reliable memory operation. This approach could potentially be applied to the next generation of non-volatile memory devices as well as in integrated system-on-glass displays.

Leakage Current Reduction Using 350-nm Ultra-Violet Irradiation in P-Channel Polycrystalline-Silicon Thin-Film Transistors

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V−1 s−1 of field-effect mobility, 190 mV dec−1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to −5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion ...