Chang Y. Choo

Hopfield network for stereo vision correspondence

An optimization approach is used to solve the correspondence problem for a set of features extracted from a pair of stereo images. A cost function is defined to represent the constraints on the solution, which is then mapped onto a two-dimensional Hopfield neural network for minimization. Each neuron in the network represents a possible match between a feature in the left image and one in the right image. Correspondence is achieved by initializing (exciting) each neuron that represents a possible match and then allowing the network to settle down into a stable state. The network uses the initial inputs and the compatibility measures between the matched points to find a stable state.

Dynamic finite-state vector quantization of digital images

A vector quantization (VQ) scheme with finite memory called dynamic finite-state vector quantization (DFSVQ) is presented. The encoder consists of a large codebook, so called super-codebook, where for each input vector a fixed number of its codevectors are chosen to generate a much smaller codebook (sub-codebook). This sub-codebook represents the best matching codevectors that could be found in the super-codebook for encoding the current input vector. The choice for the codevectors in the sub-codebook is based on the information obtained from the previously encoded blocks where directional conditional block probability (histogram) matrices are used in the selection of the codevectors. The index of the best matching codevector in the sub-codebook is transmitted to the receiver. An adaptive DFSVQ scheme is also proposed in which, when encoding an input vector, first the sub-codebook is searched for a matching codevector to satisfy a pre-specified waveform distortion. If such a codevector is not found in tile current sub-codebook then the whole super-codebook is checked for a better match. If a better match is found then a signaling flag along with the corresponding index of the codevector is transmitted to the receiver. Both the DFSVQ encoder and its adaptive version are implemented. Experimental results for several monochrome images with a super-codebook size of 256 or 512 and different sub-codebook sizes are presented. >

An efficient technique for compressing chain-coded line drawing images

An efficient technique for compressing chain-encoded line drawings is presented. The technique constructs a codebook containing vectors of chains which recur frequently in the chain-encoded line drawings. The recurrent vectors are encoded as their corresponding addresses in the codebook preceded by header bits. The encoding procedure and an efficient way to organize and label the vectors, which turns out to be somewhat similar to the generalized chain codes, are described.<<ETX>>

An efficient terrain acquisition algorithm for a mobile robot

A terrain acquisition algorithm for an autonomous mobile robot to learn and model its surrounding terrain efficiently with respect to travel distance, and sensing operations is presented. It is shown that this algorithm enables a mobile robot to visit relatively few obstacle vertices to construct a map of a planar terrain occupied by polygonal obstacles. According to this algorithm, a mobile robot travels to a vertex of the obstacles only when additional terrain information can be obtained from there. The decision to move to a vertex is thus based on whether any incident edge of a vertex is missing or occluded.<<ETX>>

A Real-Time Bit-Serial Rank Filter Implementation Using Xilinx FPGA

Rank filter is a non-linear filter used in image processing for impulse noise removal, morphological operations, and image enhancement. Real-time applications, such as video and high-speed acquisition cameras, often require the rank filter, and the much simpler median filter. Implementing the rank filter in hardware, can achieve the required speeds for these applications. Bit-serial algorithm can increase the speed of rank filter by eliminating the time-consuming sorting network. In this paper, an 8-stage pipelined architecture for rank filter is described using the bit-serial algorithm. It also includes an efficient window extraction and boundary-processing scheme. This rank filter design was simulated and synthesized on the Xilinx family of FPGAs. For 3×3 window size, the maximum operating frequency achieved was 75 MHz on a low-end device XC3S200 of Spartan-3 family, and 180 MHz on a high-end device XC4VSX25 of Virtex-4 family. For 5×5 window size, the maximum operating frequency achieved was 67 MHz on XC3S200, and 138 MHz on XC4VSX25. With a pixel filtered out at every clock cycle, the achieved speeds are sufficient for most of the video applications. The 3×3 window size design used 31% of slices on XC3S200, and 5% on XC4VSX25. The 5×5 window size design used 60% of slices on XC3S200, and 11% on XC4VSX25. This IP design may be used as a hardware accelerator in a fast image processing SOC.

A self-organizing adaptive vector quantization technique

Abstract This paper describes a new adaptive vector quantization scheme suitable for encoding monochrome and color images. In the proposed technique, a large codebook, consisting of two sections, called higher and lower priority sections, respectively, and representing common and specific characteristics of images, is designed. During encoding the entries in the two sections are reorganized and exchanged as a function of frequency of codevector usage at given intervals. The rate and the extent of adaptation are dictated by the update interval and the desired level of quality, respectively. Adaptation is achieved without requiring any transmission of the vectors themselves. The codebook is expected to adaptively self-organize itself in such a manner that the highpriority part of the codebook is sensitized to track the local (specific) characteristics of the input image. This method improves the coding efficiency and provides a perceptually more consistent image quality throughout all areas of the restructured image. Simulation results show that for the test color images bit rates in the range of 0.15–0.25 bits per pixel with a signal-to-noise ratio around 27–30 dB can be achieved.

Hierarchical block truncation coding of digital HDTV images

A source coding technique for compressing HDTV (high-definition television) digital images for B-ISDN (broadband integrated services digital network) visual services is presented. The proposed technique is called hierarchical block truncation coding (HBTC). It is a combination of the block truncation coding (BTC) technique and a quadtree segmentation method. The quadtree segmentation is used to decompose an image into homogeneous regions so that the BTC method can exploit the nonstationarity of the image data. Bit rates around 1.46 b/pixel are achieved with this method. Experimental results for several HDTV images are presented. It is shown that greater image compression can be achieved by using a hierarchical BTC method in conjunction with quadtree segmentation, than by applying BTC to an image with uniform block divisions, since the correlation of uniform areas is exploited. This is especially true for appropriate images such as HDTV with large uniform areas. >

A hashing-based scheme for organizing vector quantization codebook

One of the problems in vector quantization (VQ) is its relatively long encoding time especially when an exhaustive search is made for the codevector. This paper presents a hashing-based technique to organize the codebook so that the search time can be significantly reduced. Hashing gives the speed advantages of a direct search, while maintaining a codebook of reasonable size. Experiments show that hashing-based VQ sustained image quality as the encoding time was reduced, while full search VQ suffered greatly. For example, for 2/spl times/2 vectors and with 1024 codebook entries, encoding time was reduced by a factor of 10 without significant loss of image quality.

Object recognition by a Hopfield neural network

A model-based recognition method is introduced which is formulated as an optimization problem. An energy function is derived which represents the constraints on the best solution in order to find the best match. A two-dimensional binary Hopfield neural network is implemented to minimize the energy function. The state of each neuron in the Hopfield network represents the possibility of a match between a node in the model graph and a node in the scene graph.<<ETX>>

An FPGA-based embedded wideband audio codec system

Wideband audio codec (WAC) improves the voice quality in the hand-free communication system. It allows the telephone conversation to sound more natural and subtle. In this paper, the G.729.1 WAC is ported to Altera Nios II platform and then optimized with dedicated hardware FIR filter and MDCT accelerators to improve the performance for faster operation. The hardware FIR filter and MDCT accelerators are each designed as a customized Altera on-chip Avalon bus device to work with the Nios II embedded processor. The cores are implemented in Verilog and incorporated with the Aletra SOPC Builder. It was simulated with Altera ModelSim. The performance of the WAC with the software only and that with the hardware FIR filterbank and MDCT were compared. The embedded WAC system was implemented in the Stratix II DSP Development Kit with Altera Quartus II and Embedded Development toolset. The system currently works at 100MHz and utilizes 48% of the Altera Stratix II EP2S60 FPGA logic cell resources.