Changhao Yan
Fudan University
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Publication
Featured researches published by Changhao Yan.
international conference on computer aided design | 2013
Ye Zhang; Wai Shing Luk; Hai Zhou; Changhao Yan; Xuan Zeng
While double patterning lithography (DPL) is still in active development, triple or even quadruple patterning has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle the layout decomposition problem for general multiple patterning lithography (MPL). The main idea is to reduce the problem to sets of concurrent bi-coloring problems. The overall solution is refined iteratively by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this approach is that the existing DPL techniques can be reused seamlessly. Any improvement of them can directly benefit to the MPL counterpart. Moreover, we observe that with the help of the SPQR-tree graph division method, each pass can be fulfilled in nearly linear time. In addition, to prevent the solution getting stuck in the local minima, a randomized initialization strategy is incorporated. The PWC method is executed certain number of times with different randomized initial solutions, out of which the best solution is selected as output. We have implemented our method for particular triple patterning lithography (TPL). The experimental results show that compared with two recently published methods for TPL, our method can reduce the number of conflicts up to 33.2% and 44.9% respectively.
design automation conference | 2009
Chunyang Feng; Hai Zhou; Changhao Yan; Jun Tao; Xuan Zeng
To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the dummy fill problem as a standard Linear Program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. In this paper, we develop a dummy fill algorithm that is both efficient and with provably good performance. It is based on a fully polynomial time approximation scheme by Fleischer [4] for covering LP problems. Furthermore, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte-Carlo based heuristic methods. Experimental results demonstrate the effectiveness and efficiency of our algorithms.
design automation conference | 2008
Yi Wang; Wai-Shing Luk; Xuan Zeng; Jun Tao; Changhao Yan; Jiarong Tong; Wei Cai; Jia Ni
In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. In this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling non-Gaussian distributions of critical path delays. Firstly a general formulation of the optimization problem is proposed, which covers most of the previous formulations and indicates their limitations with statistical interpretations. Then a generalized minimum balancing algorithm is proposed for effectively solving the skew scheduling problem. Experimental results show that the proposed method significantly outperforms some representative methods previously proposed for yield optimization, and could obtain timing yield improvements up to 33.6% and averagely 17.7%.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2016
Yunfeng Yang; Wai Shing Luk; David Z. Pan; Hai Zhou; Changhao Yan; Dian Zhou; Xuan Zeng
As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and electron-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion
international symposium on quality electronic design | 2008
Yi Wang; Xuan Zeng; Jun Tao; Hengliang Zhu; Xu Luo; Changhao Yan; Wei Cai
{K}
international symposium on quality electronic design | 2008
Qiang Fu; Wai-Shing Luk; Jun Tao; Changhao Yan; Xuan Zeng
-partition problem, where
SIAM Journal on Scientific Computing | 2013
Changhao Yan; Wei Cai; Xuan Zeng
{K}
design, automation, and test in europe | 2011
Yanling Zhi; Wai Shing Luk; Hai Zhou; Changhao Yan; Hengliang Zhu; Xuan Zeng
is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2011
Chunyang Feng; Hai Zhou; Changhao Yan; Jun Tao; Xuan Zeng
{K} {=} 2
Journal of The Electrochemical Society | 2009
Chunyang Feng; Changhao Yan; Jun Tao; Xuan Zeng; Wei Cai
, we propose a primal-dual (PD) method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all “noncyclable” edges. Furthermore, we investigate two versions of the PD method, one with planarization and one without. For