Zeyi Wang

Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM

A quasi-multiple medium (QMM) method based on the direct boundary element method (BEM) is presented to extract the capacitance of three-dimensional (3-D) very large scale integration interconnects with multiple dielectrics. QMM decomposes each dielectric layer into a few fictitious medium blocks, and generates an overall coefficient matrix with high sparsity. With the storage technique of a sparse blocked matrix and iterative equation solver generalized minimal residual, the QMM can greatly reduce the CPU time and memory usage of large-scale direct BEM computation. Numerical examples of 3-D multilayered and multiconductor structures cut from actual layout show the efficiency of the QMM method for capacitance extraction. We also compared the QMM accelerated BEM with geometry independent measured equation of invariance (GIMEI) and Zhus overlapping domain decomposition method (ODDM).

Enhanced QMM-BEM solver for three-dimensional multiple-dielectric capacitance extraction within the finite domain

The computational time and memory of three-dimensional capacitance extraction have been greatly reduced by using a quasi-multiple medium (QMM) technology, because it enlarges the matrix sparsity produced by the direct boundary element method. In this paper, an approach to automatically determining the QMM cutting pair number and a preconditioning technique are proposed to enhance the QMM-based capacitance extraction. With these two enhancements, the capacitance extraction can achieve much higher speed and adaptability. Experimental results examine the efficiency of two enhancements and show over 10/spl times/ speed-up and memory saving over the multipole approach with comparable accuracy.

A two-dimensional resistance simulator using the boundary element method

A resistance simulator for extraction of the parasitic parameters from VLSI layout is presented. The calculation of the resistor network is based on the boundary element method (BEM). The computational results indicate that the BEM has an advantage over the finite difference method (FDM) and the finite element method (FEM). Since only discretized equations on the boundary of solved domain need to be solved, the grid number on the boundary is much smaller and mesh generation is greatly simplified. Hence the execution CPU time is reduced drastically. In order to treat the corners on the boundary, the concept of multiple normal derivatives at a corner is proposed. The concept is used in both continuous and partially discontinuous linear elements to increase the accuracy and reduce the number of unknowns. It is shown that a nonuniform mesh scheme is useful for problems with some stronger singularities. >

Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method

Inserting dummy (area fill) metals is necessary to reduce the pattern-dependent variation of dielectric thickness in the chemical-mechanical polishing (CMP) process. Such floating dummy metals affect interconnect capacitance and, therefore, signal delay and crosstalk significantly. To take the floating dummies into account, an efficient method for three-dimensional (3-D) capacitance extraction based on boundary element method is proposed. By introducing a floating condition into the direct boundary integral equation (BIE) and adopting an efficient preconditioning technique, and the quasi-multiple medium (QMM) acceleration, the method achieves very high computational speed. For some typical structures of area fill, the presented algorithm has shown over 1000/spl times/ speedup over the industry-standard Raphael while preserving high accuracy. Compared with the recently proposed PASCAL in the work of Park et al. (2000), the proposed method also has about ten times speedup. Since the dummies are not regarded as normal electrodes in capacitance extraction, the proposed method is much more efficient than the conventional method, especially in cases with a large number of floating dummies.

Hierarchical block boundary-element method (HBBEM): a fast field solver for 3-D capacitance extraction

As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for three-dimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.

An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation

An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency.

Improved Boundary Element Method for Fast 3-D Interconnect Resistance Extraction

SUMMARY Efficient extraction of interconnect parasitic parameters has become very important for present deep submicron designs. In this paper, the improved boundary element method (BEM) is presented for 3D interconnect resistance extraction. The BEM is accelerated by the recently proposed quasi-multiple medium (QMM) technology, which quasicuts the calculated region to enlarge the sparsity of the overall coefficient matrix to solve. An un-average quasi-cutting scheme for QMM, advanced nonuniform element partition and technique of employing the linear element for some special surfaces are proposed. These improvements considerably condense the computational resource of the QMM-based BEM without loss of accuracy. Experiments on actual layout cases show that the presented method is several hundred to several thousand times faster than the well-known commercial software Raphael, while preserving the high accuracy.

Hierarchical computation of 3-D interconnect capacitance using direct boundary element method

The idea of Appels hierarchical algorithm handling the many-body problem is implemented in the direct boundary element method (BEM) for computation of 3D VLSI parasitic capacitance. Both the electric potential and normal electric field intensity on the boundary are involved, so it can be much easier to handle problems with multiple dielectrics and finite dielectric structure than the indirect BEM. Three kinds of boundaries (forced boundary, natural boundary and dielectric interface) are treated. Two integral kernels with different singularity (1/r, 1/r/sup 3/) are involved while computing the interaction between the boundary elements. These features make it significantly distinct from the hierarchical algorithm based on the indirect BEM, which only handles single dielectric, one integral kernel and one forced boundary. The coefficient matrix is generated and stored hierarchically in this paper. As a result, computation cost of the matrix is reduced, and the matrix-vector multiplication in the GMRES iteration is accelerated, so computation speed is improved significantly.

New approaches in a 3-D one-carrier device solver

A 3-D one-carrier device solver has been developed on an Intel iPSC2 hypercube multiprocessor which can handle over 130 K nodes. CPU time averages 20 min per bias point on a 50 K-node MOSFET example. Slotboom variables are used in conjunction with the Scharfetter-Gummel current discretization scheme. A scaling scheme is proposed which produces n, p variables from the Slotboom variables. An improved damped-Newton scheme, which maintains the iteration numbers at below fifteen for high gate biases, is used in solving Poissons equation. The performance of a previously proposed initial guess scheme is improved through the use of a novel update strategy during the Poisson solution stage after the initial guess step. This improvement allows stable calculation for voltage steps as high as 5 V. A modified singular perturbation scheme (MSP) has been proposed whose implementation speeds up the convergence under high-V/sub gs/ and -V/sub ds/ bias conditions by a factor of three to six. A block matrix analysis of the MSP scheme yields insight into its performance. >

A fast quasi-multiple medium method for 3-D bem calculation of parasitic capacitance☆

Abstract A quasi-multiple medium (QMM) method is proposed to accelerate the boundary element method (BEM) for the 3-D parasitic capacitance calculation. In the QMM method, a homogeneous dielectric is decomposed into a number of fictitious medium blocks, each with the same permittivity of original medium. By the localization character of BEM, the QMM method makes great sparsity to the coefficient matrix of the overall discretized BEM equations. Then, using storing technique of sparse matrix and iterative equation solvers, the sparsity is explored to greatly reduce CPU time and memory usage of BEM computation. The computational complexity of the QMM accelerated BEM for a single-medium model problem is analyzed, and it is concluded as O ( N ), if the number of iterations is bounded. Numerical results verify the theoretical analysis and show the accelerating efficiency of the QMM method for calculation of 3-D parasitic capacitance.