Changho Seok

A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loop

This paper presents a biopotential analog front-end (AFE) IC for measuring electroencephalogram (EEG). The AFE is based on the AC-coupled chopper stabilized instrumentation amplifier architecture to achieve the low noise. To increase the input impedance, the capacitive input impedance boosting loop (CIIBL) is proposed. The CIIBL forms a positive feedback loop between input and output of the instrumentation amplifier without additional power consumption. The CIIBL increases the input impedance from 644 MΩ to 3.5 GΩ, and enhances the CMRR from 133.4 dB to 139.1 dB, in simulation. The overall gain, the frequency response, and the input mismatches can be trimmed using programmable capacitors and programmable resistors. The AFE is fabricated in 0.18 μm 1P6M CMOS process. The core chip size of the AFE without I/O pads is 4000 by 4500 μm2. The input referred noise is measured to be 0.205 μVrms in the bandwidth from 0.5 Hz to 100 Hz. The amplifying gain of the pass band is measured to be 78 dB.

Capacitive Readout Circuit for Tri-axes Microaccelerometer with Sub-fF Offset Calibration

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a chargestoring capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and 230 μA, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are 349 μg/√Hz, 341 μg/√Hz and 411 μg/√Hz, respectively.

Area-efficient RC low pass filter using T-networked resistors and capacitance multiplier

A low pass filters (LPFs) are important building blocks for many analog integrated circuit design. The biomedical applications or the sensor applications require the LPFs with very low cut-off frequency. The simplest way to implement the LPF is using the passive RC filter. The passive RC LPF, however, consumes large chip area when the desired time constant is large. The transconductance-C (gm-C) filter or the switched capacitor (SC) filters are widely used to achieve the low cut-off frequency in limited area. However, non-linearity and switching noise are major drawbacks of the gm-C filters and the SC filters. This paper presents an area-efficient LPF using T-networked resistors and current-mode capacitance multiplier. The area of the proposed LPF is reduced to 8.31 % of the conventional passive RC LPF at the same cut-off frequency of 7.1 kHz. The proposed LPF is designed using standard 0.18 μm CMOS process with the option process of high-resistivity polysilicon resistor and metal-insulator-metal capacitor.

The Micro Pirani Gauge with Low Noise CDS-CTIA for In-Situ Vacuum Monitoring

A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 ㎷ / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be 268 μV rms in 0.5 ㎐ to 50 ㎐, which is 41.2% smaller than conventional CTIA.

A 16-channel neural stimulator with DAC sharing scheme for visual prostheses

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for high resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for visual prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is 26%, compared to the conventional scheme. The stimulator IC is designed using standard 0.18 μm 1P6M process. The chip size except the I/O cells is 437 μm × 501 μm.

An analog front-end IC with regulated R-I amplifier and CDS CTIA for microbolometer

An analog front-end design that can improve the performance of the readout integrated circuit (ROIC) for the microbolometer infrared (IR) focal plane array (FPA) is presented. The analog front-end circuit for the microbolometer generally consists of the resistance-to-current (R-I) converter and the capacitive transimpedance amplifier (CTIA). The resistances of the microbolometer FPA are changed when absorbing IR. These resistance changes are converted to the output voltages by R-I converters and CTIAs. To eliminate the VTH-variations and to reduce the 1/f noise, a novel regulated R-I converter with current mirror amplifier and a correlated double sampled (CDS) CTIA are proposed. The output noise of the proposed design is -19.15 dB lower than conventional design at 1 Hz. The chip is designed using the standard 0.18 μm 1P6M CMOS process.

A versatile biopotential acquisition analog front end IC with effective DC offset and ripple rejection

This paper presents an analog front-end (AFE) IC for measuring biopotential signals such as electroencephalogram (EEG) and, electrocardiogram (ECG). The AFE employs the capacitively coupled chopper instrumentation amplifier architecture to achieve low noise. To reduce chopper ripple and respiration artifacts, a continuous-time AC-coupled ripple reduction loop (RRL) and DC servo loop (DSL) are employed. The proposed IC features differential gain of 72dB, and a common mode rejection ratio (CMRR) of 226 dB at 50 Hz, respectively. The input referred noise is simulated to be 1.6 μVrms in the bandwidth from 1 Hz to 100 Hz.

A 16-channel Neural Stimulator IC with DAC Sharing Scheme for Artificial Retinal Prostheses

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard 0.18 μm 1P6M process. The chip size except the I/O cells is 437 μm × 501 μm.