Jindeok Seo

Capacitive Readout Circuit for Tri-axes Microaccelerometer with Sub-fF Offset Calibration

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a chargestoring capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and 230 μA, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are 349 μg/√Hz, 341 μg/√Hz and 411 μg/√Hz, respectively.

Area-efficient RC low pass filter using T-networked resistors and capacitance multiplier

A low pass filters (LPFs) are important building blocks for many analog integrated circuit design. The biomedical applications or the sensor applications require the LPFs with very low cut-off frequency. The simplest way to implement the LPF is using the passive RC filter. The passive RC LPF, however, consumes large chip area when the desired time constant is large. The transconductance-C (gm-C) filter or the switched capacitor (SC) filters are widely used to achieve the low cut-off frequency in limited area. However, non-linearity and switching noise are major drawbacks of the gm-C filters and the SC filters. This paper presents an area-efficient LPF using T-networked resistors and current-mode capacitance multiplier. The area of the proposed LPF is reduced to 8.31 % of the conventional passive RC LPF at the same cut-off frequency of 7.1 kHz. The proposed LPF is designed using standard 0.18 μm CMOS process with the option process of high-resistivity polysilicon resistor and metal-insulator-metal capacitor.

A 16-channel neural stimulator with DAC sharing scheme for visual prostheses

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for high resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for visual prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is 26%, compared to the conventional scheme. The stimulator IC is designed using standard 0.18 μm 1P6M process. The chip size except the I/O cells is 437 μm × 501 μm.

An analog front-end IC with regulated R-I amplifier and CDS CTIA for microbolometer

An analog front-end design that can improve the performance of the readout integrated circuit (ROIC) for the microbolometer infrared (IR) focal plane array (FPA) is presented. The analog front-end circuit for the microbolometer generally consists of the resistance-to-current (R-I) converter and the capacitive transimpedance amplifier (CTIA). The resistances of the microbolometer FPA are changed when absorbing IR. These resistance changes are converted to the output voltages by R-I converters and CTIAs. To eliminate the VTH-variations and to reduce the 1/f noise, a novel regulated R-I converter with current mirror amplifier and a correlated double sampled (CDS) CTIA are proposed. The output noise of the proposed design is -19.15 dB lower than conventional design at 1 Hz. The chip is designed using the standard 0.18 μm 1P6M CMOS process.

Sub-fF trimmable readout circuit for tri-axes capacitive microaccelerometers

As the sensing capacitances of the recent microaccelerometers become smaller, a precise calibration method is highly required to compensate for the input parasitic capacitance mismatch. This paper presents a sub-fF trimmable readout circuit for capacitive tri-axes microaccelerometer. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to-equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous methods using series-connected capacitors. The readout circuit is implemented in a 0.18 μm 1P4M CMOS process. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and 230 μA, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are 349 μg/√Hz, 341 μg/√Hz and 411 μg/√Hz at 2 kHz bandwidth.

An Arbitrary Waveform 16 Channel Neural Stimulator with Adaptive Supply Regulator in 0.35 ㎛ HV CMOS for Visual Prosthesis

We describe a neural stimulator front-end with arbitrary stimulation waveform generator and adaptive supply regulator (ASR) for visual prosthesis. Each pixel circuit generates arbitrary current waveform with 5 bit programmable amplitude. The ASR provides the internal supply voltage regulated to the minimum required voltage for stimulation. The prototype is implemented in 0.35 μm CMOS with HV option and occupies 2.94 mm₂ including I/Os.

Frequency Response Compensation Technique for Capacitive Microresonator

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.