Changju Yang

Neural Synaptic Weighting With a Pulse-Based Memristor Circuit

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohms law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.

Memristor Emulator for Memristor Circuit Applications

A memristor emulator which imitates the behavior of a TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO2 memristor model in real circuit.

Memristor Bridge Synapse-Based Neural Network and Its Learning

Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.

Memristor Bridge Synapses

In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

Memristor-based multilevel memory

A method to utilize the memristor as a multilevel memory has been proposed. There are several roadblocks in the practical use of memristors for multilevel memory. A difficulty comes from the nonlinearity in the ¿ vs. q curve which makes it difficult to determine the proper pulse width for desired resistance values. Another one comes from the property of the memristor which integrates any kind of signals including noise that appeared at the memristor and causes memristors to be perturbed from their original values. The proposed method enables the memristor to be used as multilevel memory using a reference resistance array by forcing the memristor to stick at a set of predetermined fixed reference resistance values. We propose the write-in (programming) circuit and the readout/restoration circuit which share the information storing technique using the reference resistance array.

A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.

A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators

A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

A Generic Model of Memristors With Parasitic Components

In this paper, a generic model of memristive systems, which can emulate the behavior of real memristive devices is proposed. Non-ideal pinched hysteresis loops are sometimes observed in real memristive devices. For example, the hysteresis loops may deviate from the origin over a broad range of amplitude A and frequency f of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.

A memristor emulator as a replacement of a real memristor

In this paper, we propose a memristor emulator that embraces most of features of a real memristor. The important features that a memristor emulator should include are a sufficiently wide range of memristance, bimodal operability of pulse and continuous signal inputs, a long period of nonvolatility, floating operation, operability with other devices, and the ability to be implemented with off-the-shelf devices. The proposed memristor emulator circuit contains all of these features. Specifically, the small variation range of memristance and the nonfloating operation that limit conventional memristor emulators are improved significantly. It is designed to be built with off-the-shelf electronics devices.

Transient Behaviors of Multiple Memristor Circuits Based on Flux Charge Relationship

Memristor, a new electrical element, can have various configurations of multiple memristors, including serial and parallel connections like previous elements R, L and C. When input voltage/current is supplied to a circuit with multiple memristors, the composite behavior of the memristor circuit exhibits transient states before it enters a steady state. During the transient state period, the behavior is very complex and not predictable due to each memristors different action depending upon its connection polarity and initial state. In this paper, the transient characteristics of a composite memristor are analyzed via the relationships of charge, flux and memristance of each memristor. Also, the behavior of an individual memristor is formulated mathematically and a general computation method of composite memristance for multiple-memristor circuits of diverse configurations is proposed. Various simulations have also been performed to verify the effectiveness of the proposed method for differently configured memristor circuits, in terms of polarities and initial states.