Hyongsuk Kim

Neural Synaptic Weighting With a Pulse-Based Memristor Circuit

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohms law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.

Three Fingerprints of Memristor

This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.

Memristor Emulator for Memristor Circuit Applications

A memristor emulator which imitates the behavior of a TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO2 memristor model in real circuit.

Memristor Bridge Synapse-Based Neural Network and Its Learning

Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.

Memristor Bridge Synapses

In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

HODGKIN–HUXLEY AXON IS MADE OF MEMRISTORS

This paper presents a rigorous and comprehensive nonlinear circuit-theoretic foundation for the memristive Hodgkin–Huxley Axon Circuit model. We show that the Hodgkin–Huxley Axon comprises a potass...

Memristor-based multilevel memory

A method to utilize the memristor as a multilevel memory has been proposed. There are several roadblocks in the practical use of memristors for multilevel memory. A difficulty comes from the nonlinearity in the ¿ vs. q curve which makes it difficult to determine the proper pulse width for desired resistance values. Another one comes from the property of the memristor which integrates any kind of signals including noise that appeared at the memristor and causes memristors to be perturbed from their original values. The proposed method enables the memristor to be used as multilevel memory using a reference resistance array by forcing the memristor to stick at a set of predetermined fixed reference resistance values. We propose the write-in (programming) circuit and the readout/restoration circuit which share the information storing technique using the reference resistance array.

Brains Are Made of Memristors

This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axons of our neurons are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figures in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover, the pinched hysteresis loops for the potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel memristors are destined to be classic examples of locally-active memristors in future textbooks on circuit theory and bio-physics.

NEURONS ARE POISED NEAR THE EDGE OF CHAOS

This paper shows the action potential (spikes) generated from the Hodgkin–Huxley equations emerges near the edge of chaos consisting of a tiny subset of the locally active regime of the HH equations. The main result proves that the eigenvalues of the 4 × 4 Jacobian matrix associated with the mathematically intractable system of four nonlinear differential equations are identical to the zeros of a scalar complexity function from complexity theory. Moreover, we show the loci of a pair of complex-conjugate zeros migrate continuously as a function of an externally applied DC current excitation emulating the net synaptic excitation current input to the neuron. In particular, the pair of complex-conjugate zeros move from a subcritical Hopf bifurcation point at low excitation current to a super-critical Hopf bifurcation point at high excitation current. The spikes are generated as the excitation current approaches the vicinity of the edge of chaos, which leads to the onset of the subcritical Hopf bifurcation regime. It follows from this in-depth qualitative analysis that local activity is the origin of spikes.

A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.