Changsok Han

Noise-Shaped Residue-Discharging Delta-Sigma ADCs With Time-Modulated Pulse Feedback

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure.

A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator

This paper presents a continuous-time (CT) delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator was fabricated in a 0.13

Continuous time delta-sigma modulator with an embedded passive low pass filter

\mu \text {m}

Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA

CMOS process with an active area of 0.08

A nano-ampere 2nd order temperature-compensated CMOS current reference using only single resistor for wide-temperature range applications

\text {mm}^{2}

Noise-cancelling sturdy MASH delta-sigma modulator

. It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2 V power supply.

Time-Interleaved Noise-Coupling Delta-Sigma Modulator Using Modified Noise-Shaped Integrating Quantizer

This paper presents a methodology to improve filtering in continuous time delta-sigma modulators (CTDSMs). A first order passive low pass filter is incorporated into the delta-sigma loop with a small modification of the existing active RC integrator configuration. The delay associated with the filter is compensated without any additional active components such as opamps. The proposed scheme provides an additional first order filtering to CTDSMs, resulting in an increased immunity to out-of-band blockers. Also, it relaxes the design complexity of the preceding filters. Detailed Cadence and Matlab simulations are provided to prove the operation of the proposed scheme.

28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizer

This paper combines the benefits of the Sturdy-MASH delta-sigma modulator with the benefits of the noise-shaped integrating quantizer. By using the noise-shaped integrating quantizer, the first stage quantization error is directly extracted in time-domain without the need for any extra hardware. This removes the loading on the first loop filter, and allows accurate inter-stage gain scaling. The second loop output is also provided in a time-modulated pulse which operates a DAC at the front-end of the modulator. With the use of dual-DAC data weighted averaging, the mismatch between the front-end DACs is greatly suppressed. Detailed Matlab simulation results are provided to prove the efficiency of the proposed structure.

Continuous-time delta-sigma modulator with maximally flat signal transfer function using minimum number of DACs

This paper presents a new second-order temperature-compensated current reference which uses only one resistor. The behavior of the proposed bias circuit is analyzed in this paper, and the current reference circuits were designed and simulated in a 130 nm CMOS technology. From the simulation results, the proposed current reference achieved 327 ppm/°C in the temperature range of -30°C to +150°C, which is very wide. Its nominal current is 27 nA with a current variation of + 3% at a supply voltage of 1.2 V. Compared to a conventional first-order temperature-compensated current bias circuit designed for nano-amperes, the proposed current reference provides a current that is 4.7 times more stable over the temperature range of -30°C to +150°C. Also, the current drift from process corner variations deviates less than 3.7% from the simulation results.

A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer

A noise-cancelling sturdy multi-stage noise-shaping (NC-SMASH) structure that cancels first stage quantization error is proposed. Without any modification to existing analog blocks in the traditional sturdy MASH (SMASH) structure, adding digital noise-cancelling filters (NCFs) will cancel the first stage quantization error. This quantization error cancellation, unlike the traditional MASH structure, is less sensitive to analog loop filter matching and digital filters. This is because the leakage of the first stage quantization error is shaped by the overall noise transfer function (NTF) of the proposed NC-SMASH structure. Therefore, this technique allows using low gain opamps without signal-to-noise ratio degradation and reducing the number of the first stage quantization levels. Detailed Matlab simulation results are provided to prove the efficiency of the proposed modulator.