Nima Maghari

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

A Third-Order DT

This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active element, this quantizer is merged with the active adder. In this fashion, the multi-bit flash ADC is removed and hence the loading of the active-adder is reduced to a single continuous-time comparator. Furthermore, to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements, a bi-directional discharging scheme is proposed. As a proof of concept, the second-order loop filter with the proposed quantizer is fabricated in a 0.18 μm CMOS technology and achieves over 78 dB SNDR with an oversampling ratio of 24 and 50 MHz sampling speed. The power consumption is 2.9 mW from a 1.5 V power supply.

\Delta\Sigma

In this paper, a new second-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse) is utilized with a flash ADC. The second quantization step (fine) is implemented using a noise-shaped integrating quantizer. As a result, both high resolution and first-order noise shaping is achieved. High quantization resolution enhances the modulator stability whereas the extra order of noise-shaping improves the overall performance. The proposed ΔΣ ADC incorporating the noise-shaped two-step integrating quantizer manifests a second-order noise-shaping with a first-order loop filter. To accommodate the large number of quantization levels of the feedback-DAC, a new feedback topology is presented which uses both analog and digital signals. The prototype ADC is implemented in 0.13 μm CMOS and demonstrates peak SNDR of 70.7 dB while consuming 8.1 mW under a 1.2 V supply, with an OSR of 8 at 80 MHz sampling frequency.

Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer

This brief presents a time-domain model for the slew rate of CMOS two-stage Miller compensated operational transconductance amplifiers. The effects of both the first- and second-stage currents are considered in this model and a simple analytical expression is given in terms of the compensation and load capacitors, output voltage change, and device sizes. HSPICE simulation results are provided to show the validity of the proposed model using a 0.25-/spl mu/m CMOS technology.

A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer

An all-digital programmable and reconfigurable stochastic analog-to-digital converter (ADC) is presented in this work. This ADC directly benefits from scaling by using only digital gates and relying on an increased mismatch between minimum-sized transistors. The programmability and reconfigurability are achieved by dividing the design into eight channels. The mean of each channel is set independently using a digitally generated analog reference voltage with a 10-bit control word. The output of each channel is linearized using Gaussian linear interpolation. The entire ADC is written in Verilog and synthesized into digital standard cells using regular digital design tools. Fabricated in a 130-nm complementary metal-oxide-semiconductor process, the ADC covers signal-to-noise and distortion ratio from 28 to 34.9 dB with a programmable differential input range of 400-800 mVpp at 140 MS/s and 0.7-V supply.

An accurate analysis of slew rate for two-stage CMOS opamps

An enhanced version of Sturdy MASH (SMASH) (Maghari et al., 2006) delta-sigma modulator is proposed. This structure takes advantage of the well-known stability of the MASH structure while greatly reducing its sensitivity to imperfect circuit blocks. Furthermore, no digital noise cancellation filters are needed. Hence there is no matching requirement for the analog and digital paths. With the proposed enhancement in noise shaping, the first and second stage quantization noise experience different (thus mixed) orders of noise shaping, and the accuracy of this modulator is comparable of that of the MASH structure. Simulations results and mathematical analysis demonstrate the effectiveness of this structure.

An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells

An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

Mixed-Order Sturdy MASH Δ-Σ Modulator

In this paper a new multi-loop delta-sigma modulator is presented. This multi-loop modulator is insensitive to low gain opamps while maintaining the stability advantage. As a proof of concept, a prototype was implemented to show the functionality of this structure. Measurement results shows that with open-loop opamp gain of only 35 dB, this prototype achieves over 74 dB SNDR at oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW from a 1.2 V power supply.

Multi-loop efficient sturdy MASH delta-sigma modulators

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.

74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain

In this paper, a dynamic start-up circuit for advanced bias circuits is presented. This start-up circuit supports both power-down and power-on-reset inputs for more stable functionality, satisfying the demand of low power dissipation in suspend mode. The dynamic operation of this circuit minimizes power dissipation especially when low power design is necessary. Complete analysis of this circuit is performed to help designers with device sizes and different effects of circuit parameters. HSPICE simulations are provided to show the proper functionality and validity of this circuit using 0.18 /spl mu/m CMOS technology in 1.8 V.