Chao-Gang Wei

High Quality Ferroelectric Capacitor for FeRAM Applications

Lead zirconate titanate (PZT) based ferroelectric capacitor using lead titanate (PT) as seeding layers has been prepared on silicon wafer by an improved sol-gel method. The novel ferroelectric capacitor has high dielectric constant of about 1200, ultralow leakage current density of 0.1nA/cm 2 , high remanent polarization of 20 w C/cm 2 at coercive field of about 30kV/cm, and almost fatigue free properties. The capacitor structure can be valuable for FeRAM applications.

A Ferroelectric Capacitor Mathematical Model for Spice Simulation

A behavioral ferroelectric capacitor model based on Q-V expression with model parameters extracted from experimental hysteresis loops is proposed. A compact equivalent circuit of this model is described for spice simulation of nonvolatile memories. Excellent agreement was achieved between our measurements and simulation results. The runtime for simulation of a hysteresis loop with 10,000 points is 1.55 seconds, which is similar to 1.15 seconds for a normal capacitor.

STUDIES ON THE RELAX BEHAVIOR OF SrBi2Ta2O9 THIN FILMS

ABSTRACT Relax behavior of SrBi2Ta2O9 thin film is investigated. In very short-time scale (less than 10 μs), the relaxation curve follows the characteristics of the voltage change, due to the signal and polarization delay. After 100 μss relax time, the curve tends to be linear in logarithmic time axes, suggesting that the decay of retained polarization is logarithmic damping. Applied voltage and probe polarity can influence the relaxation curve. Higher applied voltage causes higher decay rate. This can be attributed to the depolarization field, which aggravates the retained polarizations decay. Different probe polarities cause different curves, probably due to the asymmetry of the top electrode and the bottom electrode.

FREQUENCY DEPENDENCE OF THE DIELECTRIC PROPERTIES AND COERCIVE FIELD OF PbZr0.4Ti0.6O3 THIN FILMS

ABSTRACT Frequency dependence of dielectric constant and coercive field are investigated for PbZr0.4Ti0.6O3 (PZT) capacitors. The calculations base on the in-series capacitor model show that the dielectric constant followe an universal-law dependence with various bias, which could be interpreted by constant phase model. The coercive field shows power-law dependence on the frequency in different frequency range. The fitted parameter values m increased around 150 Hz. And the m did not agree with the result of Ishibashi and Orihara theory. This suggests that the space charges also play an important role in the domain reverse.

A ferroelectric capacitor compact model for circuit simulation

A ferroelectric capacitor compact model based on physical and mathematical basis with model parameters extracted from experimental measurements is proposed. This model accounts for both main hysteresis loop and minor hysteresis loops with asymmetric nonperiodic input signals. A compact equivalent circuit of this model is described for circuit simulation. Good agreement was achieved between the measurements and simulation results over a wide range of operation.

PZT Based MFS Structure for FeFET

Fabrication and properties of lead zirconate titanate (PZT) thin films have been studied for Metal-Ferroelectric-Semiconductor FET (MFSFET) devices. PZT based MFS capacitors using lead titanate (PT) as seeding layers have been respectively prepared on p-type ⟨111⟩ and n-type ⟨100⟩ silicon wafers directly by a sol-gel method. PZT/PT films are final annealed at 650°C for 1 min in oxygen ambient using rapid thermal annealing (RTA). The measured memory windows of the MFS capacitors are about 1.8 V and 5 V under the polarization voltages of ±5 V and ±10 V correspondingly. The MFS structure can be valuable for MFSFET applications.

AN INNOVATED PROCESS OF Pt/PbTiO3/PbZr0.3Ti0.7O3/PbTiO3/Pt INTEGRATED FERROELECTRIC CAPACITORS FOR FeRAM

ABSTRACT An innovated and the typical one-mask-patterned integrated ferroelectric capacitors process with Sol-Gel deposited technique are investigated. The key improvement for the innovated route is that the ferroelectric film was etched in non-crystalline phase. Due to the etching damage, the ferroelectric and fatigue properties of the typical integrated capacitor were degradation, and the desquamation of top electrode was also existed. The uniformly Pt/PbTiO3/PbZr0.3Ti0.7O3/PbTiO3/Pt (Pt/PT/PZT/PT/Pt) integrated ferroelectric capacitor arrays with explicit and smooth side-wall were obtained by the innovated integrated process. The XRD results exhibit that the innovated integrated ferroelectric capacitor was well crystallized, and the ferroelectric film belongs to the perovskite phase. The etching degradation on the properties of the innovated integrated ferroelectric capacitor was reduced to minimize, confirmed by SEM, EDX results, the ferroelectic and fatigue properties. The innovated process can be compatible with standard complementary metal oxide semiconductor (CMOS) technique. The reliable electric properties and fine profile of patterns indicate that it can be applied in the ferroelectric random access memories and other integrated ferroelectric devices.

Key Technologies for FeRAM Backend Module

Ferroelectric random access memory (FeRAM) is believed to be the most promising candidate for the next generation non-volatile memory due to its fast access time and low power consumption. Fabrication technologies of FeRAM can be divided into two parts: CMOS technologies for circuits which are standard and can be shared with traditional IC process line, and process relating to ferroelectric which is separated with CMOS process and defined as backend module. This paper described technologies for integrating ferroelectric capacitors into standard CMOS, mainly about modeling of ferroelectric capacitors and backend fabrication technologies. Hysteresis loop of the ferroelectric capacitor is the basis for FeRAM to store data. Models to describe this characteristic are the key for the design of FeRAM. A transient behavioral ferroelectric capacitor model based on C-V relation for circuit simulation is developed. The arc tangent function is used to describe the hysteresis loop. “Negative capacitance” phenomenon at reversing points of applied voltage is analyzed and introduced to the model to describe transient behaviors of the capacitor. Compact equivalent circuits are introduced to integrate this model into HSPICE for circuit simulation. Ferroelectric materials fabrication, electrodes integration and etching are the main technologies of FeRAM fabrication process. An metal organic chemical vapor deposition (MOCVD) process is developed to fabricate high quality Pb(Zr 1-x Ti x )O 3 (PZT) films. Pt is known to cause the fatigue problems when used as electrodes with PZT. Ir is used as electrodes to improve the fatigue property of PZT based capacitors, and mechanism of the fatigue is analyzed. Hard mask is used to reduce the size of the capacitors and damage caused in etching process. In our process, Al 2 O 3 is developed as hard mask, which simplifies the FeRAM backend integration process.

MODELING SWITCHING DELAY OF FERROELECTRIC DOMAINS FOR FERROELECTRIC CAPACITOR

ABSTRACT A ferroelectric capacitor compact model based on physical basis with model parameters extracted from experimental measurements is proposed. A compact equivalent circuit of this model is presented for circuit simulation. Phenomena of hysteresis loops concerning switching delay of ferroelectric domains are described, and modification are made to the compact model to express the transient characteristics due to switching delay of ferroelectric domains. After the modification to the model, precise agreement is achieved between the measurements and simulation results over a wide range of operation.

Graphic Solution and Analysis of Voltage Distribution Between Ferroelectric Capacitor/Capacitors and Bitline Capacitance

Voltage distribution between ferroelectric capacitor/capacitors and normal capacitor in ferroelectric devices is difficult to calculate or simulate due to the complicated electrical properties of the ferroelectric capacitor. This paper presents a mathematical method combined with graphic solution to analyze the voltage distribution. Analysis of voltage distribution of different structures (1FC/1NC, 2FC, 2FC/1NC) or operation patterns is summarized. The dependence of the medial value and difference of bitline voltages between “0” and “1” state after the driving pulse of plateline on the value of Cb/Cfm has been analyzed.