Ze Jia

Pt/Pb(Zr, Ti)O3/Pt capacitor with excellent fatigue properties prepared by sol?gel process applied to FeRAM

Lead zirconate titanate (PZT) film is prepared on Pt/Ti/SiO2/Si substrate by proposed processes based on the sol–gel method and rapid thermal anneal (RTA). The ratio of Zr/Ti in the PZT film is 40/60. The PZT film has a mixture of perovskite orientations in which the (110) orientation is dominant. The Pt/PZT/Pt capacitor has remanent polarization of approximately 28.8 µC cm−2 and coercive voltage of approximately 0.76 V at 3 V voltage amplitude. The Pt/PZT/Pt capacitor has excellent fatigue properties. Switch polarizations decrease to 93.1% after 6 × 1012 switch cycles. The excellent fatigue properties result from the ameliorations of PZT/Pt interface conditions, restraining Pb volatilization and the directions of crystal domains in the RTA process. Some electric properties of the PZT capacitor proposed are contrasted with those of PZT capacitors with a different anneal process in the preparation.

Effects of anode materials on resistive characteristics of NiO thin films

This letter shows that the NiO-based structure with different anodes has different resistive switching properties. A conical conductive filament (CF) model is proposed for oxygen vacancies distributed in NiO films. Modeling analysis reveals much larger dissolution velocity of CF near anodes than near cathodes during the reset process. Different interfaces shown in Auger electron spectroscopy can be bound with the model to reveal that CF is dissolved in the structure with Pt or Au as anodes, while CF remains constant if the anode material is Ti or Al, which can explain whether switching properties occur in the specific NiO-based structures.

Modulation Effect of Lead Zirconate Titanate for Zinc Oxide Channel Resistance in Ferroelectric Field Effect Transistor

In this work, bottom-gate-type ferroelectric field effect transistors (FeFET) are fabricated. Sol-gel prepared aluminum doped zinc oxide (ZnO) and Lead Zirconate Titanate (PZT) are applied as channel and gate dielectric respectively. Uniform and dense ZnO is fabricated and good conductivity is obtained. Polarization of PZT is found to decrease after Al doped ZnO is prepared on it. Obvious modulation effects of PZT on the channel are found. Capacitance of the channel and gate dielectric stacked structure is tested. And channel resistance is found to change with the direction of remnant polarization in PZT. Mechanisms of the modulation effects are investigated.

A novel fatigue-insensitive self-referenced scheme for 1T1C FRAM

A novel self-referenced scheme without reference cell is proposed for 1T1C FRAM, which is a new solution to the access scheme for high density FRAM. It is insensitive and robust to fatigue of the FRAM cells and can overcome the challenges on reference signal design for 1T1C FRAM. Furthermore, the proposed scheme can decrease the power consumption and the die size of 1T1C FRAM, compared with conventional schemes.

NITROGEN-RICH TITANIUM NITRIDE SERVING as Pt-Al DIFFUSION BARRIER FOR FeRAM APPLICATION

ABSTRACT Nitrogen-rich titanium nitride thin films are prepared by reactive sputtering using a Ti target. Distinctively, there is only N2 introduced in the reaction chamber. The obtained thin films show (111) and (200) peaks of titanium nitride, with a titanium to nitrogen ratio of 1:1.8. When applied into Pt-Al interface, such a nitrogen-rich titanium nitride layer has prevented the diffusion of Al into Pt during 450°C forming gas annealing. The contact resistance of Al/TiN x /Pt multi-structure is low enough for integrated circuit applications. While the fabrication technique of nitrogen-rich titanium nitride is simple, it still serves as a good diffusion barrier.

IMPRINT AND FATIGUE PROPERTIES OF Pt/Pb(Zr0.4Ti0.6)O3/Pt CAPACITOR

ABSTRACT Imprint and fatigue properties of Pb(Zr0.4Ti0.6)O3film prepared by sol-gel spin coating method in Pt/PZT/Pt capacitors are studied in this experiment. The voltage shift of hysteresis loops of Pt/PZT/Pt capacitors under DC voltage bias and fatigue stress are investigated at room temperature. It is shown that the absolute values of voltage shift of hysteresis loops decrease with the increasing positive bias voltage. Both the absolute and relative shifts of coercive voltage increase with the increase of fatigue stress. The properties above can be explained by the formation and change of oxide layer at PZT/electrode interface under fatigue stress and correlative theories and models.

Study of Iridium Bottom Electrode in Ferroelectric Random Access Memory Application

Iridium (Ir) is comprehensively investigated for application in Ferroelectric random access memory. Ir thin films are treated at different temperature and examined to investigate the effects of thermal processes which are unavoidable in fabrication of ferroelectric films. Stress in as deposited Ir films is found to be relieved by 400°C baking in the air. IrO2 starts to form when the temperature reaches 600°C. Then IrO2/Ir electrode formed by 650°C rapid thermal process (RTP) and Ir are used as bottom electrodes in sol-gel lead zirconium titanate (PZT) based capacitors. Effects of bottom electrodes on PZT films are investigated and electrical properties of sol-gel PZT based capacitors including polarization, fatigue and leakage are studied. Capacitors using IrO2/Ir bottom electrodes are found to have larger remnant polarization and better fatigue property. Mechanism for fatigue is studied based on oxygen vacancies according to the effects of IrO2. Leakage performance is investigated from the viewpoint of electrode work functions, which are proposed to be principal factor affecting leakage performance. Besides, surface conditions of the electrodes are examined. Roughness increase and hillock formed at the surface of Ir during thermal process may be another reason to affect leakage current.

Key Technologies for FeRAM Backend Module

Ferroelectric random access memory (FeRAM) is believed to be the most promising candidate for the next generation non-volatile memory due to its fast access time and low power consumption. Fabrication technologies of FeRAM can be divided into two parts: CMOS technologies for circuits which are standard and can be shared with traditional IC process line, and process relating to ferroelectric which is separated with CMOS process and defined as backend module. This paper described technologies for integrating ferroelectric capacitors into standard CMOS, mainly about modeling of ferroelectric capacitors and backend fabrication technologies. Hysteresis loop of the ferroelectric capacitor is the basis for FeRAM to store data. Models to describe this characteristic are the key for the design of FeRAM. A transient behavioral ferroelectric capacitor model based on C-V relation for circuit simulation is developed. The arc tangent function is used to describe the hysteresis loop. “Negative capacitance” phenomenon at reversing points of applied voltage is analyzed and introduced to the model to describe transient behaviors of the capacitor. Compact equivalent circuits are introduced to integrate this model into HSPICE for circuit simulation. Ferroelectric materials fabrication, electrodes integration and etching are the main technologies of FeRAM fabrication process. An metal organic chemical vapor deposition (MOCVD) process is developed to fabricate high quality Pb(Zr 1-x Ti x )O 3 (PZT) films. Pt is known to cause the fatigue problems when used as electrodes with PZT. Ir is used as electrodes to improve the fatigue property of PZT based capacitors, and mechanism of the fatigue is analyzed. Hard mask is used to reduce the size of the capacitors and damage caused in etching process. In our process, Al 2 O 3 is developed as hard mask, which simplifies the FeRAM backend integration process.

Modeling and analysis of effect on bit-line voltage caused by imprint in FeRAM

This study analyzed the effect on the bit-line voltage of imprint degradation in FeRAM. The hysteresis loop of the ferroelectric capacitor fitted by the three-line piecewise linear approximation model is proposed here to establish the relationship between bit-line voltage and imprint. Formulas are derived from this model for approximately calculation of the variation of bit-line voltage along with imprint voltage. The results show a linear dependence of the bit-line voltage on the imprint, and the scope of this linear relationship are determined by the parameters extracted from the hysteresis loop. The results also show that the ferroelectric capacitor with a more rectangular hysteresis loop shows less variation of the bit-line voltage according to imprint.

Investigation on Annealing and Etching Effects for Pt/Bi3.15Nd0.85Ti3O12/Pt Ferroelectric Capacitors

The annealing and etching effects of Pt/Bi3.15Nd0.85Ti3O12/Pt ferroelectric capacitors were studied. Bi3.15Nd0.85Ti3O12 (BNdT) thin films were obtained by a sol–gel method. At an annealing temperature of 650 °C, BNdT films crystallized well in nitrogen atmosphere, but remained amorphous in oxygen atmosphere. For capacitor fabrication, Pt top layers were etched by ion beam etch (IBE) to form top electrodes, and the BNdT ferroelectric films were etched by reactive ion etch (RIE) utilizing two different gases: SF6 and HC2ClF4. Degradation was discovered after top electrode etching, and could be partly recovered by rapid thermal annealing in oxygen at 650 °C. RIE etching damage was not prominent in both groups, though SF6 etched group was a bit superior to HC2ClF4 group. Nevertheless, HC2ClF4 group became noticeable inferior to SF6 group after a furnace annealing in nitrogen at 650 °C for 40 min. This was attributed to the influence of hydrogen, which was induced by RIE process in HC2ClF4 group. Instead, when oxygen was employed as the atmosphere of furnace annealing, both groups finally possessed similar ferroelectric properties, namely the RIE etching damage in HC2ClF4 group had been recovered.