Chao-Wen Tseng

Testing for resistive opens and stuck opens

This paper studies the behavior of stuck and resistive open defects. The effects on test results of three test conditions (supply voltage, speed, temperature) as well as test patterns applied are evaluated. Diagnosis schemes for stuck and resistive opens are also presented. Five Murphy chips are diagnosed as having stuck open defects and one chip is diagnosed as having a resistive open defect. Their experimental data match our expectations for stuck opens and resistive opens.

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery.

MINVDD testing for weak CMOS ICs

A weak chip is one that contains flaws-defects that do not interfere with correct circuit operation at normal conditions but may cause intermittent or early-life failures. MINVDD testing can detect weak CMOS chips. The minvdd of a chip is the minimum supply voltage value at which a chip can function correctly. It can be used to differentiate between good chips and weak chips. In the first part of this paper, we will study several types of flaws to demonstrate the effectiveness of MINVDD testing. Experimental results show that MINVDD testing is as effective as VLV testing for screening out burn-in rejects. In the second part of this paper, we propose test conditions for low voltage testing, including test voltage, test timing and test sets. Experimental results are presented to validate our proposal.

Cold delay defect screening

Delay defects can escape detection during the normal production test flow; particularly if they do not affect any of the long paths included in the test flow. Some delay defects can have their delay increased, making them easier to detect, by carrying out the test with a very low supply voltage (VLV testing). However, VLV testing is not effective for delay defects caused by high resistance interconnects. This paper presents a screening technique for such defects. This technique, cold testing, relies on carrying out the test at low temperature. One particular type of defect, silicide open, is analyzed and experimental data are presented to demonstrate the effectiveness of cold testing.

Experimental results for IDDQ and VLV testing

An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, including IDDQ failures, Very-Low-Voltage (VLV) failures, timing-independent combinational (TIC) defects, and non-TIC defects. We used 2 supply voltages for VLV tests. Two test speeds were used at each supply voltage. 9 dies failed only the VLV Boolean tests, and 7 of these were confirmed to have had high IDDQ measurement results. We also investigated the defect classes of the test escapes for 100% single stuck fault (SSF), transition fault, and IDDQ test sets.

An evaluation of pseudo random testing for detecting real defects

Research has shown that single stuck-at fault (SSF) N-detect test sets are effective for detecting defects not modeled by the SSF model. Experimental results showed N-detect coverage is a good metric for determining test quality. In this paper, we examine the test quality of pseudo-random Built-in-Self-Test (BIST) patterns by quantifying the relations between their N-detect coverage and test length. We theoretically derive bounds on the minimum test length of pseudo-random patterns required to achieve a given N-detect coverage. For faults with high detectability, the expected test length for N-detection is around N times the expected test length for single detection. However, for faults with low detectability, the expected test length for N-detection can be NlogN times the expected test length for detecting the fault only once; this increases the test length significantly. We also introduce the idea of effective detectability which is important for analyzing the effectiveness of BIST techniques for detecting real defects.

Experimental results for slow-speed testing

This paper presents slow-speed testing results for two test chip experiments at Stanford CRC: Murphy and ELF35. The test speed for slow-speed testing is 1/3 of the characterized speed, at which the circuit-under-test (CUT) can operate. At nominal supply voltage, 3 out the 116 defective Murphy CUTs escaped slow-speed testing. In the ELF35 experiment, I out of the 218 defective combinational CUTs escaped slow-speed testing. The experimental data also show that the number of test escapes depends more on the quality of the applied test sets, than on the test speed at which the test sets were applied We also evaluated the effectiveness of VLV testing at characterized speed. Our results show that it missed only one defective Murphy CUT. It detected all the defective ELF35 combinational CUTs. The one defective Murphy CUT that escaped VLV testing at characterized speed is a suspected resistive open. Schmoo characterization results show it can be detected by VLV testing at characterized speed if lot-to-lot re-characterization is done to determine the VLV testing speed.

Test chip experiments at stanford CRC

The idea of the test chip experiments started in ITC 1991 [McCluskey 00]. We wanted to get actual tester data that would answer some questions about manufacturing test of digital ICs. The objective was to find out the relative effectiveness of different test techniques, such as stuck fault tests, delay tests, IDDq, etc.