Phil Nigh

Built-in current testing-feasibility study

A testing methodology which applies built-in current sensors to detect abnormal currents in the power buses of functional blocks of CMOS ICs is proposed, that significantly improves the quality of VLSI circuit testing. A summary of simulation results and design experiments is presented to demonstrate the feasibility and to illustrate the applicability of the approach. The results suggest that built-in current testing could be a very powerful tool for overcoming basic bottlenecks in VLSI testing, providing very inexpensive testing, high-quality built-in testing, or on-chip concurrent reliability testing for high-quality fault-tolerant systems.<<ETX>>

Test generation for current testing (CMOS ICs)

Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout.<<ETX>>

Test generation for current testing

Current testing has been found to be useful for testing CMOS ICs because it can detect a large class of manufacturing defects. The concept of current testing is described; the classes of defects detectable by current testing and the conditions to detect a given defect are described; and a general test-vector generation algorithm for current testing is developed and applied to two examples.<<ETX>>

Layout-driven test generation

Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n).<<ETX>>

A self-testing ALU using built-in current sensing

A CMOS ALU (arithmetic logic unit) chip containing built-in current (BIC) sensors, which perform self-testing of the ALU, is described. The performance of two ALUs (one with and one without a BIC sensor) is analyzed by using externally applied test vectors and linear feedback shift register for BIC and for stuck-fault testing. The results demonstrate that the BIC testing methodology is well suited for initial die testing of CMOS ICs as well as for concurrent self-testing of highly reliable systems

Current signatures for production testing [CMOS ICs]

The concept of the current signature has been proposed as a means for improving testing resolution over single-threshold Iddq testing. This paper postulates a practical methodology for applying the current signature concept for die selection in a production environment.