Charles André

First Experiments Using the UML Profile for MARTE

A UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) has been recently standardized by the OMG. This initiative meets the needs of several Thales divisions (e.g., aerospace, land and joint and air systems), which develop real-time and embedded systems. CEA LIST, INRIA and Thales have been the main contributors to the MARTE standard through the ProMARTE consortium. To foster the deployment of MARTE in Thales divisions, we have launched the development of a case study related to a real-time and embedded system using the MARTE adopted specification. As a first step of this study, we make use of a fictive system- the Josefil challenge-to evaluate whether the profile is applicable to the Thales current systems and software engineering practices. The purpose of this paper is to report on this first stage and outline the next scheduled activities.

Marte CCSL to Execute East-ADL Timing Requirements

In the automotive domain, several loosely-coupled Architecture Description Languages (ADLs) compete to provide a set of abstract modeling and analysis services on top of the implementation code. In an effort to make all these languages, and more importantly their underlying models, interoperable, we use the UML Profile for MARTE as a pivot to define the semantics of these models.In this paper, we particularly focus on East-ADL2. We discuss the benefits of having an integrated, MARTE-centered, approach. We give a formal semantics of East-ADL2 timing requirements. Relying on this semantics, several kinds of analysis are possible. Requirements become executable and simulations are run. A constraint solver is used to detect logical inconsistencies. Our proposal is illustrated on an Anti-lock Braking System (ABS).

Computing SyncCharts Reactions

SYNCCHARTS are a state-based visual synchronous model. Though using a simple graphical syntax, SYNCCHARTS may exhibit complex instantaneous behavior, mixing concurrent evolutions, preemptions and state re-incarnations. This paper explains such reactions in terms of microsteps. The underlying semantics is a constructive semantics, fully compatible with the ESTEREL’s semantics. The semantics is presented in a semi-formal way, as resulting from the cooperation of concurrent reactive cells.

The clock constraint specification language for building timed causality models

The uml Profile for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by Unified Modeling Language (UML2) and offers a broad range of capabilities required to model RTE systems including discrete/dense and chronometric/logical time. The Marte specification introduces a Time Structure inspired from several time models of the concurrency theory and proposes a new clock constraint specification language (ccsl) to specify, within the context of the uml, logical and chronometric time constraints. A semantic model in ccsl is attached to a (uml) model to give its timed causality semantics. In that sense, ccsl is comparable to the Ptolemy environment, in which directors give the semantics to models according to predefined models of computation and communication. This paper focuses on one historical model of computation of Ptolemy [Synchronous Data Flow (SDF)] and shows how to build SDF graphs by combining uml models and ccsl.

A multiform time approach to real-time system modeling; Application to an automotive system

In the context of an effort to answer the OMG RFP for modeling and analysis of real-time embedded systems (MARTE), we are defining extensions to the simple time model of UML2. After a brief review of some time-related UML profdes, we focus on the specificity of our approach: the ability to take account of multiform time - concept inherited from reactive system modeling. Using an example from the automotive industry, we illustrate the use of our profile to represent, to constraint and to analyze behaviors depending on multiform time.

VHDL observers for clock constraint checking

Logical time has proved very useful to model heterogeneous and concurrent systems at various abstraction levels. The Clock Constraint Specification Language (CCSL) uses logical clocks as first-class citizens and supports a set of (logical) time patterns to specify the time behavior of systems. We promote here the use of CCSL to express and verify safety properties of VHDL designs. Our proposal relies on an automatic transformation of a CCSL specification into VHDL code that checks the expected properties. Being written in VHDL this code can be integrated in a classical VHDL design and verification flow. Our proposed structural transformation assembles instances of pre-built VHDL components while preserving the polychronous semantics of CCSL. This is not trivial due to major differences between the discrete-time delta cycle based semantics of VHDL and the fixed point semantics of CCSL. This paper describes these differences and proposes solutions to deal with them so as to build VHDL observers for the kernel CCSL constraints. We illustrate the approach by verifying an open-source implementation of the AMBA AHB-to-ABP bridge.

On the Semantics of UML/MARTE Clock Constraints

The UML goal of being a general-purpose modeling language discards the possibility to adopt too precise and strict a semantics. Users are to refine or define the semantics in their domain specific profiles. In the UML Profile for MARTE, we devised a broadly expressive Time Model to provide a generic timed interpretation for UML models. Our clock constraint specification language supports the specification of systems with multiple clock domains. Starting with a priori independent clocks, we progressively constrain them to get a family of possible executions. Our language supports both synchronous and asynchronous constraints, just like the synchronous language Signal, but also allows explicit non determinism. In this paper, we give a formal semantics to a core subset of MARTE clock constraint language and we give an equivalent interpretation of this kernel in two other very different formal languages, Signal and Time Petri nets.

Leveraging patterns on domain models to improve UML profile definition

Building a reliable UML profile is a difficult activity that requires the use of complex mechanisms -stereotypes and their attributes, OCL enforcement- to define a domain-specific modeling language (DSML). Despite the ever increasing number of profiles being built in many domains, there is a little published literature available to help DSML designers. Without a clear design process, most such profiles are inaccurate and jeopardize subsequent model transformations or model analyses. We believe that a suitable approach to building UML based domain specific languages should include systematic transformation of domain representations into profiles. This article therefore proposes a clearly-defined process geared to helping the designer throughout this design activity. Starting from the conceptual domain model, we identify a set of design patterns for which we detail several profile implementations. We illustrate our approach by creating a simplified profile that depicts elements belonging to a real-time system domain. The prototype tool supporting our approach is also described.

Structural Transformations Giving B-Equivalent PT-Nets

In two previous papers, we introduced the notion of the B-equivalence (equivalence of behaviour) of two PT-nets on a common subset of transitions [Andre 80] and we pointed out the interest of the substitution theorem in PT-net analysis [Andre 81-2]. In short, the substitution of a closed subnet by a B-equivalent one doesn’t change the properties (liveness, synchronic relations for transitions; markings for places) on the unmodified part of the net.

Executing AADL Models with UML/MARTE

AADL and MARTE are two modeling formalisms supporting the analysis of real-time embedded systems. Since both cover similar aspects, a clear assessment of their respective strength and weakness is required. Building on previous works, we focus here on the time aspects of the two specifications. Relying on the MARTE Time Model and the operational semantics of its companion language CCSL we attempt to equip UML activities with the executionsemantics of an AADL specification. This is part of a muchbroader effort to build a generic simulator for UML modelswith the semantics explicitly defined within the model.