Frédéric Mallet

Modeling time(s)

Time and timing features are an important aspect of modern electronic systems, often of embedded nature. We argue here that in early design phases, time is often of logical (rather than physical) nature, even possibly multiform. The compilation/synthesis of heterogeneous applications onto architecture platforms then largely amounts to adjusting the former logical time(s) demands onto the latter physical time abilities. Many distributed scheduling techniques pertain to this approach of time refinement.n We provide extensive Time and Allocation metamodels that open the possibility to cast this approach in a Model-Driven Engineering light. We give a UML representation of these concepts through two subprofiles, parts of the foundations of the forthcoming OMG UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE). Time modeling also allows for a precise description of time-related entities and their associated timed properties.

Clock constraint specification language: specifying clock constraints with UML/MARTE

The Object Management Group (OMG) unified modeling language (UML) profile for modeling and analysis of real-time and embedded systems (MARTE) aims at using the general-purpose modeling language UML in the domain of real-time and embedded (RTE) systems. To achieve this goal, it is absolutely required to introduce inside the mainly untimed UML an unambiguous time structure which MARTE model elements can rely on to build precise models amenable to formal analysis. The MARTE Time model has defined such a structure. We have also defined a non-normative concrete syntax called the clock constraint specification language (CCSL) to demonstrate what can be done based on this structure. This paper gives a brief overview of this syntax and its formal semantics, and shows how existing UML model elements can be used to apply this syntax in a graphical way and benefit from the semantics.

The clock constraint specification language for building timed causality models

The uml Profile for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by Unified Modeling Language (UML2) and offers a broad range of capabilities required to model RTE systems including discrete/dense and chronometric/logical time. The Marte specification introduces a Time Structure inspired from several time models of the concurrency theory and proposes a new clock constraint specification language (ccsl) to specify, within the context of the uml, logical and chronometric time constraints. A semantic model in ccsl is attached to a (uml) model to give its timed causality semantics. In that sense, ccsl is comparable to the Ptolemy environment, in which directors give the semantics to models according to predefined models of computation and communication. This paper focuses on one historical model of computation of Ptolemy [Synchronous Data Flow (SDF)] and shows how to build SDF graphs by combining uml models and ccsl.

VHDL observers for clock constraint checking

Logical time has proved very useful to model heterogeneous and concurrent systems at various abstraction levels. The Clock Constraint Specification Language (CCSL) uses logical clocks as first-class citizens and supports a set of (logical) time patterns to specify the time behavior of systems. We promote here the use of CCSL to express and verify safety properties of VHDL designs. Our proposal relies on an automatic transformation of a CCSL specification into VHDL code that checks the expected properties. Being written in VHDL this code can be integrated in a classical VHDL design and verification flow. Our proposed structural transformation assembles instances of pre-built VHDL components while preserving the polychronous semantics of CCSL. This is not trivial due to major differences between the discrete-time delta cycle based semantics of VHDL and the fixed point semantics of CCSL. This paper describes these differences and proposes solutions to deal with them so as to build VHDL observers for the kernel CCSL constraints. We illustrate the approach by verifying an open-source implementation of the AMBA AHB-to-ABP bridge.

Specification and verification of time requirements with CCSL and Esterel

The UML Profile for Modeling and Analysis of Real-Time and Embedded (MARTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and offers a broad range of capabilities required to model real-time systems including discrete/dense and chronometric/logical time. MARTE OMG specification introduces a Time Structure inspired by Time models of the concurrency theory and proposes a new clock constraint specification language (CCSL) to specify, within the context of UML, logical and chronometric time constraints.n This paper introduces the formal semantics of a fundamental subset of CCSL clock constraints and proposes a process to use CCSL both as a high-level specification language for UML models and as a golden model to verify the conformance of implementations with the specification.n A digital filtering video application is used as a running example to support the discussion. The application is first formally specified with CCSL and the specification is refined based on feedback from our CCSL-dedicated simulator. In a second phase, an Esterel program of the application is considered. This program is instrumented with observers derived from the CCSL specification. Esterel Studio formal verification facilities are then used to check the conformity of the Esterel implementation with the CCSL specification. A specific library of Esterel observers has been built for this purpose.

MARTE: a profile for RT/E systems modeling, analysis-- and simulation ?

As its name promises, the Unified Modeling Language (UML) provides a collection of diagrammatic modeling styles. To the early class/objects and use-case diagrams were almost immediately added state-, activity-, collaboration-, and component diagrams. All these modeling views, required for structural and behavioral representations of systems, were then progressed to further detailed expressivity. Provision for domain-specific specializations was made under the form of profiles. n nSomehow this goal of being rather universal and extendible discarded the possibility of UML to adopt too strict and precise a semantics; as users were generally to define and refine it in their stereotyped profiles anyway. As a result, even the little execution semantics there is in the standard is often not considered in such specializations. n nWe tackled the general issue of defining a broadly expressive Time Model as a sub-profile of the upcoming OMG Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE), currently undergoing finalization at OMG. The goal is to provide a generic timed interpretation, on which timed models of computation and timed simulation semantics could be built inside the UML definition scope, instead of as part of the many external proprietary profiles. The MARTE time library can be used as the basis for the definition of a UML real-time simulator.

Logical time at work: Capturing data dependencies and platform constraints

Data-flow models are convenient to represent signal processing systems. They precisely reflect the data-dependencies and numerous algorithms exist to compute a static schedule that optimizes a given criterion especially for parallel implementations. Once deployed the data-flow models must be refined with constraints imposed by the environment and the execution platform. In this paper, we show how we can model data dependencies supported by multi-dimensional synchronous data flow with logical time and extend these data dependencies with additional logical constraints imposed by the environment. Making explicit these external constraints allows the exploration of further solutions during the scheduling computation.

An automated process for implementing multilevel domain models

Building a UML profile is tedious and error-prone. There is no precise methodology to guide the process. Best practices recommend gathering concepts in a technology-independent domain view before implementation. Still, the adequacy of the implementation should be verified. This paper proposes to transform automatically a domain model into a profile-based implementation. To reduce accidental complexity in the domain model and fully benefit from advanced profiling features in the generated profile, our process relies on the multilevel paradigm. The value of this paradigm for the definition of uml profiles is assessed and applied to a subset of the marte time model.

IP-XACT components with abstract time characterization

Large system-on-chips are built by assembly of components modeled at different representation levels (TLM, RTL). The IP-XACT standard focuses on structure, type and memory information and ignores behavior and time issues. The UML profile for MARTE and its companion language CCSL provide advanced time modeling capabilities. By combining UML MARTE and IP-XACT, we introduce a more abstract timed representation level allowing the description of IP-XACT designs with UML-based environments. This paper discusses the use of MARTE to annotate IP-XACT specifications with time requirements. These time requirements are first used in simulation to generate waveforms. Then, actual implementations are considered and adequate observers are generated to validate these implementations with respect to the MARTE specification. The proposal is illustrated on the Leon2 architecture and specifically on its AHB to APB bridge.

Hardware architecture modelling using an object-oriented method

The very high integration rate and the increasing complexity of digital hardware architectures and embedded applications lead designers to search for new tools and methods. In order to reduce the time-to-market it becomes essential to allow designers to evaluate performances of a given application with the targetted architecture very soon in the design phase. So we have decided to build a modelling simulation environment in order to evaluate the requisite number of cycles for processing a given application with a simple model of a digital hardware architecture. Then, our main objective and the greatest part of our work is to describe this environment with an example based on the Pine DSP and some classical digital signal processing applications: FIR, FFT butterfly, Viterbis Butterfly.