Charles Augustine

Spin-Based Neuron Model With Domain-Wall Magnets as Synapse

We present artificial neural network design using spin devices that achieves ultralow voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nanomagnets for modeling neuron and domain-wall magnets for compact, programmable synapses. The spin-based neuron-synapse units operate locally at ultralow supply voltage of 30 mV resulting in low computation power. CMOS-based interneuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics-based models developed for the spin devices. Simulation results for character recognition as a benchmark application show 95% lower power consumption as compared to 45-nm CMOS design.

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the bit-cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Greens Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM bit-cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and bit-cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM bit-cells with results in agreement with experiments.

Low-power functionality enhanced computation architecture using spin-based devices

Power consumption in CMOS integrated circuits increases every technology generation due to increased subthreshold and gate leakage currents. To cope with such a problem, researchers have started looking at the possibility of logic devices based on electron spin, as an alternative to charge based CMOS, for realizing low-power integrated circuits with low active power dissipation and zero standby leakage. In this paper, we investigate spin-based logic devices that employ low-power spin-torque switching mechanism for circuit operation. We have developed a Functionality Enhanced All Spin Logic (FEASL) architecture and a synthesis framework using Logically Passively Self Dual (LPSD) formulation. This methodology enables the design of large functional logic blocks, especially low-power adders and multipliers, which constitute the building blocks of all arithmetic logic units (ALU). In addition, we have investigated three different variants of ASL, which are low-power, medium-power—medium performance and high performance and we analyze their merits and drawbacks at circuit/architecture level. We synthesized Discrete Cosine Transform (DCT) algorithm using adders and multipliers to show the efficacy of the proposed FEASL approach in designing digital signal processing (DSP) systems. Compared to 15nm CMOS implementation, the FEASL based DCT shows 88% improvement in power and 83% in PDP with 43% degradation in performance.

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRAM, DRAM and flash memories. It also solves the key drawbacks of conventional MRAM technology: poor scalability and high write current. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we developed an efficient simulation tool to capture the coupled electro/magnetic dynamics of spintronic device, leading to effective prediction for memory yield. We also developed a statistical optimization methodology to minimize the memory failure probability. The proposed methodology can be used at an early stage of the design cycle to enhance memory yield.

Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits

A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau-Lifshitz-Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-in-built voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators.

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Numerical analysis of domain wall propagation for dense memory arrays

This paper presents numerical analysis of domain wall propagation for dense embedded memory applications. Self-consistent simulation framework based on Four Component Spin Transport Model and Landau-Lifshitz-Gilbert equation is able to capture domain wall motion in terms of critical current density requirement, domain wall velocity, and power dissipation. Effect of patterned notches on memory stability, domain wall velocity and nanostrip resistance are also presented. Finally, the proposed simulation framework is used to investigate performance, scalability and organization of the domain wall motion based memory structure.

Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation

In recent years, spin-transfer torque magnetoresistive random access memory (STT-MRAM) has gained a lot of interest as a promising memory candidate for future embedded applications. STT-MRAM possesses desirable memory attributes such as excellent readability, writability, stability, non-volatility, and unlimited endurance. Moreover, ITRS reports that STT-MRAM can endure 1015 cycle operations before breakdown [1] thus meeting 10 yrs life-time. As shown in Fig. 1, STT-MRAM bitcell consists of one access transistor and one magnetic tunnel junction (MTJ) (1T-1R). One of the primary reliability concerns in STT-MRAM is the dielectric breakdown of the tunnel junction MgO in the MTJ known as time-dependent dielectric breakdown (TDDB). The thickness of MgO is on the order of 1nm and the voltage across the MTJ during write operation is approximately 0.7V resulting in electric field of ∼10MV/cm across it which can induce TDDB [2–3]. Thus, such high stress conditions can lead to lower breakdown time (TBD) which can go even lower with further MgO thickness scaling. In addition to the hard breakdown (HBD) in MTJ which results in very low MTJ impedance and inability to function as memory, experimental results show that soft breakdowns (SBD) also exists [7,8]. SBDs cause minor degradation in the MTJ resistance and they have shorter average time to appear compared to HBDs. In this paper, we explore in detail the physical mechanism behind both HBD and SBD, and using percolation model we estimate the time dependent degradation in the MTJ performance parameters such as tunneling magneto-resistance (TMR), write current (JC), write-time (TWR) and lifetime (TLIFE).

Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions

Electronic transport and magnetization dynamics associated with the current induced spin torque effects in dual barrier magnetic tunnel junctions (MTJs) have been investigated using nonequilibrium Green’s Function equations solved self-consistently with Landau–Lifshitz–Gilbert–Slonczewski equation. In a dual barrier (pentalayer) MTJ, a set of geometry and band-structure parameters jointly determines the position of resonant peaks and valleys within the energy range of interest. The presence of nonmonotonic quantum well states inside the central ferromagnetic free layer significantly modifies the critical switching voltage across MTJ and tunneling magnetoresistance simultaneously depending on whether the resonant condition is satisfied. Proper choice of (i) free ferromagnetic layer thickness, (ii) tunneling barrier height, (iii) width of the tunneling barrier, and (iv) operational voltage has been found to increase both in-plane and out-of-plane spin torque efficiencies in pentalayer MTJs by approximately ...

A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems

CMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay and optimistic assumption) over 45nm CMOS in energy consumption and area, respectively.